Hi
I want to implement an image processing algo using verilog... I have a design module that calculates histogram of image and gives 2 output 'nout' and 'x'. nout is no.of pixels in a bin while x is centre of bin. i have 10 elements of nout and x each for 10 bins each nout of 12 bits and x of 8 bits. i declared it in verilog as:
module myimhist(nout,x,y,nbin);
parameter length_nout=12; //length of nout
parameter length_xxy=8; //length of x
parameter length_nbin=4; //length of nbin
parameter depth=10;
but it gives syntax error when simulated in modelsim for the 2 outputs..... can anybody help me out that how to out these two registered outputs???
Plz reply as soon as possible.
hey,can any one please help me how to convert multidimensional array into one dimensional array....
i'm new in FPGA and using system generator in matlab..
i want to get camera data into a FPGA...
since its RGB it has dimensions of [mxnx3]
but the GATE IN block allows only one dimension
so can u plz help me to solve the problem
hey,can any one please help me how to convert multidimensional array into one dimensional array....
i'm new in FPGA and using system generator in matlab..
i want to get camera data into a FPGA...
since its RGB it has dimensions of [mxnx3]
but the GATE IN block allows only one dimension
so can u plz help me to solve the problem