Implementing FIFO code in a FPGA with VHDL

[Rosluc]

Hi everyone!

I'm a basic (extremely basic!) vhdl programmer and I have to implement a FIFO code in an FPGA (Spartan 3) with VHDL.
The code I written seems to work untill the "pointer" (an integer that stores where in the array the system has to write the data) miss a +1 for some reason I'm not able to understand....

Is there some one who has some good example code for a FIFO?

And, btw, what happens to a signal integer range 0 to 7 when is at 7 and it is increased of one?

Thank you a lot for you answer

 

[FvM]

Re: Vhdl FIFO

And, btw, what happens to a signal integer range 0 to 7 when is at 7 and it is increased of one?

In simulation, the overflow causes an execption. In synthesis, it can be expected to be implemented as 3 bit unsigned and roll over to 0.

 

[Rosluc]

Re: Vhdl FIFO

And, btw, what happens to a signal integer range 0 to 7 when is at 7 and it is increased of one?

In simulation, the overflow causes an execption. In synthesis, it can be expected to be implemented as 3 bit unsigned and roll over to 0.

First of all thank you for the answer.
I've tried to display the value and it seems allright, I mean that after the "7" I got a "0", that exactly what I want!

The problem, anyway, still remail.... seems like for reasons I'm not able to understand the code "skip" some line of a process sometime....

I mean In the FIFO i have 3 "counters", a pointer for the reading one for the writing and one for storing the number of element memorized... they are increased and decreased in the code but sometimes it doesn't happen.
Anyone got any clue?

Thanks