Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Implementing FIFO code in a FPGA with VHDL

Status
Not open for further replies.

Rosluc

Newbie level 2
Joined
Jan 19, 2010
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
france
Activity points
1,297
Hi everyone!

I'm a basic (extremely basic!) vhdl programmer and I have to implement a FIFO code in an FPGA (Spartan 3) with VHDL.
The code I written seems to work untill the "pointer" (an integer that stores where in the array the system has to write the data) miss a +1 for some reason I'm not able to understand....

Is there some one who has some good example code for a FIFO?

And, btw, what happens to a signal integer range 0 to 7 when is at 7 and it is increased of one?

Thank you a lot for you answer :)
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
49,167
Helped
14,396
Reputation
29,056
Reaction score
13,147
Trophy points
1,393
Location
Bochum, Germany
Activity points
283,353
Re: Vhdl FIFO

And, btw, what happens to a signal integer range 0 to 7 when is at 7 and it is increased of one?

In simulation, the overflow causes an execption. In synthesis, it can be expected to be implemented as 3 bit unsigned and roll over to 0.
 

Rosluc

Newbie level 2
Joined
Jan 19, 2010
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
france
Activity points
1,297
Re: Vhdl FIFO

FvM said:
And, btw, what happens to a signal integer range 0 to 7 when is at 7 and it is increased of one?

In simulation, the overflow causes an execption. In synthesis, it can be expected to be implemented as 3 bit unsigned and roll over to 0.

First of all thank you for the answer.
I've tried to display the value and it seems allright, I mean that after the "7" I got a "0", that exactly what I want!

The problem, anyway, still remail.... seems like for reasons I'm not able to understand the code "skip" some line of a process sometime....

I mean In the FIFO i have 3 "counters", a pointer for the reading one for the writing and one for storing the number of element memorized... they are increased and decreased in the code but sometimes it doesn't happen.
Anyone got any clue?

Thanks :)
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top