implementing equations

[pritin]

how to implement the following function in verilog

Δ = clip ( -c , c , ((q0-p0)<<2 + (p1-q1)+4)>>3)
where clip(a,b,c) is a clipping function that clips c to a value b/w a and b.

 

[echo47]

Your equation is somewhat unclear, needs more parenthesis.
You didn't say what type variables those are. I'll assume 16-bit signed values.

How about this?

module top (c, p0, q0, p1, q1, delta);
  input signed   [15:0] c, p0, q0, p1, q1;
  wire signed    [15:0] temp;
  output signed  [15:0] delta;

  assign temp = (((q0 - p0 + 0) <<< 2) + p1 - q1 + 4) >>> 3;
  assign delta = (temp < -c) ? -c : (temp > c) ? c : temp;
endmodule

Or maybe this:

module top (c, p0, q0, p1, q1, delta);
  input signed   [15:0] c, p0, q0, p1, q1;
  output signed  [15:0] delta;

  function signed [15:0] clip;
    input signed [15:0] a, b, c;
    clip = (c < a) ? a : (c > b) ? b : c;
  endfunction

  assign delta = clip(-c, c, (((q0 - p0 + 0) <<< 2) + p1 - q1 + 4) >>> 3);
endmodule

Beware, hastily-written and untested!