Implementing an soft core inside FPGA

[sadid]

I'm designing an FPGA based embeded system I have not enough time...but I need a general purpose system inside current design.
Is it take much time?
for example implementing Nios II @ Apex -Altera


another question?
is it possible to find a OSPF protocol implemention code in an HDL Language?
is there anyone who has done sth similar? isn't it too time-consuming?

 

[davorin]

If you would have checked https://www.altera.com/literature/hb/nios2/n2cpu_nii51015.pdf you would know NIOS2 isn't supported on APEX device....

For OSPF or any router related stuff have a read at:

https://www.embeddedrelated.com/usenet/embedded/show/91649-1.php


If you figure out to do a OSPF on a single FPGA don0t forget to sell it for big bucks to Cisco and Juniper (o;

 

[sadid]

I know ....
OSPF RFC has more than 200page....
but I don't want to implement it...I can use it over a general purpose system inside the FPGA....
this is why some companies like CISC@ hasn't implement such router inside a FPGA .... they implement protocols in an OS like IOS over thier platform...
but thank , I'll have done the job by next friday so ...