Implementing a MIPS on FPGA using verilog

[discovers.rohit]

I am trying to implement pipelined MIPS using verilog on FPGA.
But while doing simulation, xylinx gives an error and says that the design can't be compiled due to specific coding constructs .
I consulted site of xylinx for this and it told me that xylinx is actively working on reducing the no. of instances for this error and cited some work arounds for getting over with this error. I tried some of them like simplifying the code a bit and not passing complex instructions as parameters to any function.....
But there was no effect and still the same error was displayed .....
And also i was not able to understand some workarounds...
can someone help me?


"Error: Simulator:606 - ISE Simulator is unable to compile this design due to
specific coding constructs used in design unit work/copy, defined in file
"C:/Users/Rohit/Desktop/comp arch/pipelined_mips/copy.v". Xilinx is actively
working on reducing the number of conditions where this error occurs. For
more information on this error, please consult Answer Record 24068 in Answers
Database at https://www.xilinx.com/support. "

link-- https://www.xilinx.com/support.

 

[ssk1]

what exact simpliication or modification in the code you made ...and you got the same error ? cant help your problem without knowing wht changes you hav made in the code

 

[bapodradhairyab]

please paste portion of code where you are facing this error, it may help in replying you appropriate answer...