Implementing a LUT with VHDL's DDS Compiler

[ckelly4]

Hey guys, I am working on a design project which requires sine wave frequencies from MATLAB to be implemented into VHDL as a LUT. I am using the DDS Compiler to generate the sine waves but am unsure as to how to put in a LUT for the values. It is an 8-bit output sine wave which is outputted to a DAC, I use a Spartan3E FPGA.

Any help is greatly appreciated, and if you need more info just ask.

 

[lucbra]

You will need a block of RAM that takes the values of your calculations.

The LUT that was referred to is a LookUp Table, not the LUT that is a hardware part of a logic element within an FPGA.

 

[FvM]

I don't particularly know the Xilinx DDS compiler, but similar tools from other vendors are generating the full DDS design, including LUT or alternative sine generation schemes. You just enter the specification: frequency and amplitude resolution, clock rate and features (e.q. quadrature output, AM, FM etc.). You don't need Matlab or manual LUT generation.

I'm sure, the user manual will tell about the details.

 

[ckelly4]

I don't particularly know the Xilinx DDS compiler, but similar tools from other vendors are generating the full DDS design, including LUT or alternative sine generation schemes. You just enter the specification: frequency and amplitude resolution, clock rate and features (e.q. quadrature output, AM, FM etc.). You don't need Matlab or manual LUT generation.

I'm sure, the user manual will tell about the details.

Are these similar tools compatible with VHDL? What are their names? Thanks.

 

[FvM]

I was thinking e.g. of the Altera DDS compiler, which is basically a core generator, similar to the Xilinx product. The generated core can be included in VHDL or Verilog designs.

 

[ckelly4]

Yes but unfortunately the Altera DDS Compiler cannot be opened in Xilinx VHDL.

 

[mrflibble]

Yes but unfortunately the Altera DDS Compiler cannot be opened in Xilinx VHDL.

Use xilinx core generator => DDS Compiler. That you can use in your vhdl based projects in xilinx ISE.

And if all you want is a sin/cos, then the DDS Compiler will do all that for you. LUT will be generated for you, no need to bother with matlab...

 

[white85]

Hello everybody!

I am with Xilinx ISE 13.3 and would like to implement a DDS with an asynchronous clear input. The IP Core DDS v5.0 would fullfill my expectations, but unfortunately it seems like it is only available for Xilinx ISE 7 or older versions.

In Xilinx ISE 13.3 I can only find the core DDS Compiler, you mentioned. But it doesn't have any ACLR. Does anybody know if is there any chance to use DDS v5.0 with ISE 13.3?

And if not, how could I create a new imput ACLR in the DDS Compiler IP Core?

Thank you

 

[mrflibble]

If an async clear is the only thing you feel is missing, and for the rest the newer core does everything you want ... You can use the newer core and add a synchronizer for the clear input. That is, you have an async clear somewhere in your design. So synchronize it, and send the synchronized reset to the DDS core.

That's probably less hassle than trying to get the IP Core DDS v5.0 under ISE 13.3.

 

[FvM]

And if not, how could I create a new imput ACLR in the DDS Compiler IP Core?

Honestly speaking, I'm not motivated to think about doubtful ideas without at least a reasonable justification.

 

[HimaNshu Korde]

can u give me the detailed info of this project and please tell me abt the sofware used in it

 

[mrflibble]

Install recent version of xilinx ISE, then use xilinx core generator => DDS Compiler.

 

[HimaNshu Korde]

from which site can we get this xilinx software ISE 13.3 and how it could be implimented
and can i have the a detailed discussion on this topic .
my facebook ID is deyanroyal@gmail.com
or simply search Himanshu Korde
or u can give me ur ID or name also
Thnak you.

 

[mrflibble]

Why would I want to search that, when you can google where you can download ISE? The mind boggles.