first step would be to have the algorithm working in something like C or Matlab so you have some form of reference model.
Then architect the algorithm so that it works on an FPGA.
Your post is rather vague, and lacking in detail. What have you done so far and what are you having trouble with?
We arnt here to complete the work for you, but we can help with specific problems.
If you have no digital logic experience, then you're really going to struggle.
You might have to have a look at Xilinx HLS or Altera's OpenCL compilers, as they may be able to convert your C to an FPGA implementation. While this may not produce the most optimal solution, it should give you something that will work on an FPGA - but note you will still need an understand of how an FPGA works.
This may be something a little too advanced as a first foray into the world of FPGAs.
I didn't ask someone to complete the work for me ! All I want is to get help and know how to start to implement this framework.
I think you didn't get what I meant, I want to run a C program on FPGA instead of CPU, not converting the program.
By converting the C program to HDL there is no need for implementing a framework on FPGA and definitely it is not optimal.
Any C program run on an FPGA is either run on a processor (far slower then your PC processor) or you have to use a C to gates conversion a.k.a. Xilinx HLS or Altera's OpenCL compilers already mentioned by Tricky.
If you go the route of C program to HDL you are still going to have to know how FPGAs work and as Tricky says this may be more than you can handle as a first time FPGA user. Don't be misled by the marketing hype about jumping straight from being a C software coder and becoming a full fledged FPGA expert using HLS.
If the algorithm cannot be parrellelised, then it will be slow, or even slower on an FPGA. FPGAs work best with large data sets that can be parrallelised or efficiently pipelined.
If you do not understand VHDL, or FPGA fabric, then you need to start by getting a good book/training course on digital logic design, otherwise you will go nowhere. writing VHDL is nothing at all like software, but requires a good understanding of the underlying hardware.
So - my advice, learn VHDL and FPGA archutecture first (this could be 12+months study) before attempting to convert an algorithm to VHDL.
without knowing your system we cannot really comment in what you need
That's what I was talking about!
I've done some works with Xilinx FPGAs and somehow I'm familiar with VHDL. In this particular case, I don't understand how to convert the algorithm steps to digital blocks, it's really confusing. For instance, you can code the graph nodes easily with linked list in C and you traverse the nodes one by one. But what is the equal block for describing a node in VHDL? :thinker:
Algorithms that have things like linked lists and such, which are easily implemented in software are typically not something a novice at FPGAs should take on.
I've converted software algorithms into hardware and they end up looking like some sort of microcode machine (basically a dedicated hand made processor for the specific task).
Other algorithms end up being a huge very complex pipelined design that runs at some multiple of the clock (due to things like read modify write requirements of the data being manipulated).
In either case they can potentially run faster than a software implementation running on a multi-GHz processor, but they are hardly something a novice can tackle. The last two designs that I implemented were really software algorithms both had >20 stage pipelines with one having 3 phases of the clock used for various operations read/calc/write to RAM for each piece of processed data along with that pipeline (i.e. >60 clock cycles before the operation was completed on the first input data). Tracking all the stages and the keeping the pipeline was a headache. It would have been better to do those designs with simulink or HLS, but in both cases they were not available, so I had to code it all in Verilog, not something I would recommend doing. If your design requires information based on previous data then you might have an even more clock cycles than my 3 clocks per data, basically you need to store stuff for later use by the pipeline, it can get very convoluted very quickly.
My recommendation if it can be done using a higher level of abstraction, i.e. HLS, or simulink then do it. Take the hit on performance. If you go the route I used to "optimize" the design you will be in way over your head as a novice at FPGAs.
So your suggestion is to convert the algorithm by means of HLS or any similar way, but do you think it really takes effect on performance?
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