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implementing a delay in FPGA

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delay

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create delay in fpga

Hi all,

If I absolutely need to introduce a delay in for a physical circuit on a FPGA chip, how can I do it knowing synthesizers usully toss dalays out?

delay (delayed by technology)
 

bupteda

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hi,delay
I don't know if your system can introduce a clock with it's period just the same as the delay you want,if so,u can implement your specified delay circuit by simply sample your signal to be delayed.Otherwise,it's always useless to write sentences such as 'after' in VHDL or '#' in verilog to delay a signal or wire.
By the way,if you choose Altera as your FPGA provider as I do,a way that's not recommened by Altera to implement delay is to use the component or module 'LCELL' which is included in Altera's library lpm.
 

ramesh

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For small delay (order of nano seconds), use gates (Ex: AND, OR or BUFFERS).
 

mc&fpga

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most of hdl synthesiser if you select speed or area to synthesise they delete the componet that make delay,if you want to make a delay if it isn't small make it by clk( like a counter),and if it's small(ns) make by component like buffers and some other ways.how much is the delay that you want to make?
 

Husoo

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first, consider if delay is really needed. And consider again...

if delay falls into the domain of one of your applied clocks then choose ff, shift register or counter to implement the delay.

if you are not able to use clock, synthetizers can prevent objects from being optimized.
Eg.: Synopsis FPGA Express supports for "dont_touch"
Set this attribute on a module/entity/design and also on cells and instances. Setting this attribute prevents that portion of the design from being optimized, effectively treating it as a black box.

attribute dont_touch of Clk_inv1 : label is "true";
 

tlp71@hotmail.com

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if you have a high frequency clock you can buffer your signal in a fifo where you can set the delay whiuc you like to add at you r signal.
The gate and buffer soluction is very hard to manage, in fact every p&R can change your delay.
bye.
G.
 

dll_embed

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Route your signal out and link it back will give u a fixed amount of delay.
 

ashishjindal76

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for small delay u can use buffers and for long delay u can use counter or shift register

regards
Ashish
 

elektrom

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See page 6 on Xilinx's application note XAPP688. It's about building delay element using LUTs in FPGA.
 

bibo1978

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If you want to know the delay of your design and know how a LUT for example introduce a delay you can not depend on synthesis results, you can use the post PAR behavoral model with the standard delay file to get an approximation of the estimated delay, any synthesis tool simply won't give the right results "I haven't use physical synthesis tools yet but I guess that it can give a better results"
 

huster

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Use a high frequency clock is the only way.
 

bibo1978

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Another technique of introducing delay "if you are using a high end FPGA like Xilinx VirtexII pro" you can introduce the delay through the clock rather rathar than through the signal this is more advantageous because you can exactly fine tune the delay as required, this can be done using the DCM I believe that this is the most trustable solution. if you have a problem in interfacing between the two clock doamins then you should try to put a asynchrounous FIFO.

If the DCM is not available "like Virtex" then you can use two clock refrences as i/ps one delayed from each other by the required amount "try a PLL AD41 series "3 $" or 2 DDS 10 $", still you will have to manage the two clock domains interface "Asynchronous FIFO is just the most suitable solution usually"

thats all folks
 

Al Farouk

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The best way is to use FIFO and design it as a separat component and when instantiat it into your design instruct the synthesizer to "Not Optimize" theis component so it remains as it is keeping the equivalent number of clock cycles you want to delay.
 

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