implementation pipeline cpu with verilog

[bidgol]

verilog pipeline

hi friends
Please excuse me for bad english!
i need a presentaion or book that how implement pipeline cpu with hdl(verilog).
pls help me.
thanks

 

[staraimm]

pipelined cpu verilog

You can learn the pipeline cpu design from the open project:
https://www.opencores.com/pnews.cgi/list/or1k?no_loop=yes

 

[pramodm]

pipeline verilog

for a simple pipeline cpu design u can refer any HDL(verilog) book

verilog hardware description language by moorby has a simple example on processor design

 

[bidgol]

implementation of pipelining using verilog

i design a no-pipeline cpu with vhdl. but i need a instruction that illustrate a Implementation of pipeline cpu with verilog step by step.
i thanks for your help.