implementation of real time clock on fpga

[the moon is back]

hi, is it possible to design and implement a real time clock on fpga using vhdl hardware descriptive language?

 

[TrickyDicky]

yes.
you can now mark this solved.

 

[shaiko]

Sure you can.
But it would only be as percise as the FPGA clock oscilator you're using

 

[the moon is back]

thank u, but a real time clock should work even if the fpga is in off condition, but as i know once we switch off the fpga, the code downloaded on fpga wil get erased then how come it keep working when fpga is off? pls help me in this.

 

[verylsi]

In such cases where we need non volatile memory, we can use an interfaced PROM and download mcs file into it. By configuring FPGA through PROM we don't need to reprogram it.
I believe thats ur solution.

 

[shaiko]

a real time clock should work even if the fpga is in off condition

That's impossible. Once the FPGA's core voltage is disconnected - the logic functionality becomes unsustainable.
However, there're FPGA's out there that consume very little power. This may eliminate the need to shut them down completely.

Check out Actel's IGLOO nano and IGLOO plus.
Being FLASH devices, they are very low power and don't require an external PROM to load from.

Finally, you should know that although FPGAs are very flexible and usefull devices, they will probably never reach the low power levels possible with full custom ASICs.
Therefore, if you need a "smart" device with the lowest possible power consumption - you should probably go for an MCU like Microchip's PIC or TI's MSP430. Some have embedded RTCs inside them.


verylsi,
I believe that the requirement is for a constantly running RTC - not for a nonvolatile loading source for the FPGA.

 

[the moon is back]

ok thank u very much for your information.