Implementation of FFT

Status
Not open for further replies.

sougata_vlsi13

Member level 5
For Implementation of 8 point radix 2 FFT butterfly structure is cordic needed for realization of its structure or just a complex multiplier is sufficient to solve the problem of complex addition and subtraction in VHDL.

syedshan

hi.

I have done previously FFT but not implementing it from the core, are you aware that there are cores available for it as well..
Like when you are using xilinx FPGAs, then you can use coregen to generate the FFT core...

I know this does not answer your question, but may save your time and effort much if you can use the substitute.

sougata_vlsi13

sougata_vlsi13

points: 2

sougata_vlsi13

Member level 5
I agree with you......& also I am aware with the fact the readymade cores are available....but actually i need to write the code.....so in that regard i need help about what to do...

TrickyDicky

First of all, makesure you have a matlab model of the design.
Then write the VHDL
Then compare the Matlab results to VHDL simulation.

Then program it into the chip.

xtcx

To start with, use Xilinx IP for FFT first and then you may try to create one yourself. Also as Tricky said, you should use Matlab design side by side for design.

sougata_vlsi13

Member level 5
actually please tell me what is meant by matlab design.....are you people talking about system generator

TrickyDicky

You need some initial model or algorithm design to make sure the algorithm works. Matlab is one method, or you could implement it in C. whatever, you need something to compare the VHDL to.

sougata_vlsi13

Member level 5
ok...but in matlab where it i available...means is it readymade in matlab that design...bcoz currently i m referring the data sheet of xilinx ip core FFT version 8...is that would be helpful

syedshan

you have to make it in matlab, you will find loads of example in matlab, generate, for example, a sine wave, do FFT over it(look matlab help) and save result in .txt file

simulatanously save the text file for the sine wave data as well and input it to the verilog or VHDL code to input to your FFT model in simulation level, and then compare the result. This is what I did when I was doing FFT

sougata_vlsi13

Member level 5
But here sir the problem is that i have never gone through matlab software....is it really necessary to run the matlab for the FFT....i intend to write the code in VHDL....nd as per ip generation i m referring the pdf of FFT 8.0..am i going in correct path...?

syedshan

not necessary, but how ill you verify that the result that you have generated from the VHDL code is right or wrong, you need to have some set of data to verify, if not matlab, use labview, or C language...

btw matlab and labview are quite easy to start with, I also did not used much matlab when I was doing my FFT, and learn using it...

sougata_vlsi13

Member level 5
yes sir i also understand of what you are talking about.............ok i will try to do it in matlab.But now one problem is coming through core generator o/p is not coming.I am attaching the snapshot and core template here...please help me in this regard.please also tell me whether i can use xilinx system generator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--use UNISIM.VPKG.ALL;

entity FFT_rg1 is
port (
sclr1 : in STD_LOGIC :='1';
rfd1 : out STD_LOGIC;
start1 : in STD_LOGIC := '1';
fwd_inv1 : in STD_LOGIC := '1';
dv1 : out STD_LOGIC;
done1 : out STD_LOGIC;
clk1 : in STD_LOGIC;
busy1 : out STD_LOGIC;
scale_sch_we1 : in STD_LOGIC := '1';
fwd_inv_we1 : in STD_LOGIC := '1';
edone1 : out STD_LOGIC;
xn_re1 : in STD_LOGIC_VECTOR ( 31 downto 0 ):= "00000000000000000000111000010101";
xk_im1 : out STD_LOGIC_VECTOR ( 31 downto 0 );
xn_index1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
scale_sch1 : in STD_LOGIC_VECTOR ( 5 downto 0 ):="000011";
xk_re1 : out STD_LOGIC_VECTOR ( 31 downto 0 );
xn_im1 : in STD_LOGIC_VECTOR ( 31 downto 0 ):="00000000000000000000110000010101";
xk_index1 : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
end FFT_rg1;

architecture behav of FFT_rg1 is

component FFT_rg
port (
clk: in std_logic;
sclr: in std_logic;
start: in std_logic;
xn_re: in std_logic_vector(31 downto 0);
xn_im: in std_logic_vector(31 downto 0);
fwd_inv: in std_logic;
fwd_inv_we: in std_logic;
scale_sch: in std_logic_vector(5 downto 0);
scale_sch_we: in std_logic;
rfd: out std_logic;
xn_index: out std_logic_vector(2 downto 0);
busy: out std_logic;
edone: out std_logic;
done: out std_logic;
dv: out std_logic;
xk_index: out std_logic_vector(2 downto 0);
xk_re: out std_logic_vector(31 downto 0);
xk_im: out std_logic_vector(31 downto 0));
end component;
begin
yo : FFT_rg
port map (
clk => clk1,
sclr => sclr1,
start => start1,
xn_re => xn_re1,
xn_im => xn_im1,
fwd_inv => fwd_inv1,
fwd_inv_we => fwd_inv_we1,
scale_sch => scale_sch1,
scale_sch_we => scale_sch_we1,
rfd => rfd1,
xn_index => xn_index1,
busy => busy1,
edone => edone1,
done => done1,
dv => dv1,
xk_index => xk_index1,
xk_re => xk_re1,
xk_im => xk_im1);
end behav;

and modelsim snapshot is
please tell me why the o/p is not coming

Attachments

• 207.5 KB Views: 8

syedshan

did you write any test bench...?

you just posted me the instantiated core. There will be no output if you do not have any suitable inputs(which is given by testbench)

sougata_vlsi13

Member level 5
but sir inspite of writing the test bench i have given directly the inputs at the entity...and one more problem is coming use unisim.vpkg.all is showing the error that unisim doesnt know about this but this pkg has already created during the core gen....

sougata_vlsi13

Member level 5
sir,I have written the test bench of FFT but still the o/p is not coming even for 100 clock cycle....plz tell me what can i do now..

- - - Updated - - -

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

entity test_bn_fft is
end test_bn_fft;

architecture behav of test_bn_fft is

component top_fft
port (
clk1: in std_logic;
sclr1: in std_logic;
start1: in std_logic;
xn_re1: in std_logic_vector(31 downto 0);
xn_im1: in std_logic_vector(31 downto 0);
fwd_inv1: in std_logic;
fwd_inv_we1: in std_logic;
scale_sch1: in std_logic_vector(5 downto 0);
scale_sch_we1: in std_logic;
rfd1: out std_logic;
xn_index1: out std_logic_vector(2 downto 0);
busy1: out std_logic;
edone1: out std_logic;
done1: out std_logic;
dv1: out std_logic;
xk_index1: out std_logic_vector(2 downto 0);
xk_re1: out std_logic_vector(31 downto 0);
xk_im1: out std_logic_vector(31 downto 0));
end component;

--inputs
signal clk:std_logic:='1';
signal sclr1:std_logic:='1';
signal start1:std_logic:='1';
signal xn_re1:std_logic_vector(31 downto 0):="00000000000000000000111000010101";
signal xn_im1:std_logic_vector(31 downto 0):="00000000000000000000110000010101";
signal fwd_inv1:std_logic:='1';
signal fwd_inv_we1:std_logic:='1';
signal scale_sch1:std_logic_vector(5 downto 0):="000011";
signal scale_sch_we1: std_logic:='1';

--outputs

signal rfd1: std_logic;
signal xn_index1: std_logic_vector(2 downto 0);
signal busy1: std_logic;
signal edone1: std_logic;
signal done1: std_logic;
signal dv1: std_logic;
signal xk_index1: std_logic_vector(2 downto 0);
signal xk_re1: std_logic_vector(31 downto 0);
signal xk_im1: std_logic_vector(31 downto 0);

--clock period definitions
constant clk_period:time:=1000 ns;

begin
DUT:top_fft port map (
clk1 => clk,
sclr1 => sclr1,
start1 => start1,
xn_re1 => xn_re1,
xn_im1 => xn_im1,
fwd_inv1 => fwd_inv1,
fwd_inv_we1 => fwd_inv_we1,
scale_sch1 => scale_sch1,
scale_sch_we1 => scale_sch_we1,
rfd1 => rfd1,
xn_index1 => xn_index1,
busy1 => busy1,
edone1 => edone1,
done1 => done1,
dv1=> dv1,
xk_index1 => xk_index1,
xk_re1 => xk_re1,
xk_im1 => xk_im1);

clk_process rocess
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

main_process(clk)
begin
sclr1<='1';
start1<='1';
fwd_inv1<='1';
fwd_inv_we1<='1';
xn_re1<= "00000000000000000000111000010101";
xn_im1<="00000000000000000000110000010101";
scale_sch_we1<='1';
scale_sch1<="000011";
--wait on sclr,start,fwd_inv,fwd
end process;
end behav;

sougata_vlsi13

Member level 5
sir plz help me regarding the above problem

syedshan

hi

read the specification of the FFT core that you have developed, then you will know the workings of the signals input, when to make certain inputs high, then low...similarly there should be one outputs will get high indicating that the next cycle is valid data cycle, things like this....read the specification sheet, then try to see your results...
then write back...try to write you code here within code tags so that it is easy for us to read and understand...

btw,
where is the unload signal, you should have unload signal if you are using version 7.1 of fft core generation...
This signal when asserted High from outside, will start unloading the data....I donot see this signal

Also try not to use scaling for now...
also I do not see the RFD (Ready For Data) signal....which is needed to be high duting LOAD operation....
I urge you to re-read the data sheet then write back

sougata_vlsi13

Member level 5
I want to get rid of complex addition,subtraction and multiplication in VHDL in FFT.so for that purpose i use cordic.I need to know that should i have to use that rotation part of cordic in order to get rid of complex multiplication.please help me

Izhar Ahmed

Newbie level 6
I want to get rid of complex addition,subtraction and multiplication in VHDL in FFT.so for that purpose i use cordic.I need to know that should i have to use that rotation part of cordic in order to get rid of complex multiplication.please help me
Try reading Files on spiraj FFT

Status
Not open for further replies.