Implementation of AXI UART16550 with RS-422

[arminb73]

Hello,

I am to create a connection between AXI UART16550 and RS-422. I am to use the IP from the Xilinx library but am having a hard time configuring it to do as I want. Would really like to be able to send UART data with different baud rates. How can I accomplish this?

So far my block design in IP Integrator in Vivado looks like the following:

Most of these connections have been made automatically, and I have not used any form of "engineering" knowledge.. And I really don't know where it is to be added.

 

[ads-ee]

The "engineering" comes with reading the documentation and understanding what each component does and how it works.

https://www.xilinx.com/support/docu...on/axi_uart16550/v2_0/pg143-axi-uart16550.pdf

The BRG (Baud Rate Generator) is describe in the IP documentation.

 

[FlyingDutch]

Hello,

the block design looks OK - it should work. You can made basic configuration in IP Core "AXI_UART". You can configure "AXI_UART" programatically using "M_AXI_GP0" port (by AXI interconnect and slave AXI port "S_AXI" in IP core "AXI_UART". You can package your block design as IP Core and then eksport hardware to Xilinx SDK or Vitis (depending on the Vivado version). Then you have to write software for PS in for example SDK, what is more complicated. One think more it is a good idea to link interrupt fro UART to Zynq PS (and then handle UART interrupt in software).

I can recommend you series of tutorials about AXI bus and Zynq programming (it is very good but all lasts about several hours):

Best Regards

 

[dpaul]

Most of these connections have been made automatically, and I have not used any form of "engineering" knowledge.. And I really don't know where it is to be added.
In that case I would say that you do not have a clear picture regarding the design you want to create. Please follow what others have suggested in the above posts.
Your focus should be on Chapter5 and Chapter6 on the docu link posted by ads-ee.