Apr 27, 2018 #1 W wittman Newbie level 2 Joined Apr 25, 2018 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 21 Hi, to implement N DFF with one single clock, we can use for loop. For example Code: parameter N; integer i; reg [N-1 : 0] dff_cell, dff_cell_next; always @(posedge clk) for(i=0;i<100;i=i+1) dff_cell[i] <= dff_cell_next[i]; But, how to implement N DFF with N different clock by for loop (or other method)? Because there is error message if i write such code Code: parameter N; for (i=0;i<=100;i=i=1) always @(posedge clk[i]) ........ The parameter "N" will be config by other user, so I can make sure what it will be.
Hi, to implement N DFF with one single clock, we can use for loop. For example Code: parameter N; integer i; reg [N-1 : 0] dff_cell, dff_cell_next; always @(posedge clk) for(i=0;i<100;i=i+1) dff_cell[i] <= dff_cell_next[i]; But, how to implement N DFF with N different clock by for loop (or other method)? Because there is error message if i write such code Code: parameter N; for (i=0;i<=100;i=i=1) always @(posedge clk[i]) ........ The parameter "N" will be config by other user, so I can make sure what it will be.
Apr 27, 2018 #2 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 It has to be in a generate statement.
Apr 27, 2018 #3 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,549 Helped 397 Reputation 794 Reaction score 463 Trophy points 1,363 Activity points 14,765 I struggle to find a reason one would want to do this but... yes, use the generate statement.
Apr 27, 2018 #4 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,409 Helped 14,749 Reputation 29,780 Reaction score 14,095 Trophy points 1,393 Location Bochum, Germany Activity points 298,048 Consider that most FPGA have limited number of clock networks, if the clocks are actually different, the 100 DFF design implementation may fail.
Consider that most FPGA have limited number of clock networks, if the clocks are actually different, the 100 DFF design implementation may fail.