implemantation hierachy in ise xilinx

[mailan]

what to do if the simulation hierarchy files are similar to that of the implementation?.,i believe that there should be no testbench file in implementation hierarchy,.,thank you,.


-tstbnch_fifo (tstbnch_fifo.v)
-TOPFIFO - top_fifo (top_fifo.v)
submodules

 

[ads-ee]

Don't know if you figured this out on your own, but in ISE you have to specify what your top level module you're implementing is, so you can include the simulation files in your file hierarchy. I think you have to add them if you use ISIM (which I haven't used as I use Modelsim). I've noticed some of the example designs from Xilinx have the design plus testbench files included in the hierarchy.