Impedance matching in LVDS signalling

[Acido Cinico]

Dear friends,

I need your help for an LVDS question.
According to your direct experience,
how important is impedance matching
in VHDL signalling at 150Mbps and for
a 1m distance point to point communication?
How much the eye pattern will close
if I don't respect the 100 Ohm differential
impedance specification? I can just match
the trace/wire lengths and force the diff.pairs
to run close enough to each other.

Let me know your opinions and experiences.

Regards,
A.C.

 

[Acido Cinico]

Re: LVDS Signalling

Another question for you:

in point to point, board to board, LVDS communications, has
anyone experience in placing series resistors on ground
signals in order to minimize ground bounce?
Such a solution is used in RS485 connections.

Let me know.
A.C.

 

[zape]

LVDS Signalling

I have used LVDS links for connecting two boards at a distance greater than 3 meters, working at 175 MHz. It works fine. No series termination used, and I am not sure about the goodness of its use taking into account the input differential threshold, current driver capabilities...

 

[BuBEE]

LVDS Signalling

Dear All

I would like to know about your LVDS signal.

Did you mean LVDS from FPGA port or form LVDS IC .

 

[Acido Cinico]

Re: LVDS Signalling

I'm using LVDS for communication between FPGAs on different boards.
I'm experiencing loss of lock problems on the PLLs when I get 10 or more FPGAs in chain.
Any help?

 

[zape]

LVDS Signalling

Could you better explain your design? A diagram could help.
Are you using a multidrop configuration?

 

[Acido Cinico]

Re: LVDS Signalling

I'm not using a multidrop configuration but multiple
point-to-point connections. Each board has an RX
section and a TX section that retransmits the same
data received.[/img]

 

[zape]

LVDS Signalling

I guess you are serializing the data, so that you recover the clock in each "RX" block with the data and you are feeding the "TX" block with the recovered data and clock, is it true?

Could you detail the TX/RX blocks? What about data coding?

 

[Acido Cinico]

Re: LVDS Signalling

No, clock is not extracted from data. A differential pair is used to
transmit clock from one board to the next in chain while 5 other pairs
are used just for data and sync. So, data coding is not crucial.
What happens is a PLL loss of lock when the total number of boards
in chain is 10 or more.
I thought it could be a power supply problem - too much noise on
the PLL supply - but, after a lot of different tests, I can exclude it.

 

[zape]

LVDS Signalling

Sorry I don't see where/why you are using the PLL.

 

[Acido Cinico]

Re: LVDS Signalling

The PLLs are integrated in the FPGAs in each board.
Each board has got one FPGA. Each FPGA has a PLL
that locks on the incoming LVDS clock signal (~20MHz)
and reads the serial LVDS data. A new clock signal
(in-phase with that data) is retransmitted to the next-in-chain
board.

 

[zape]

LVDS Signalling

"Acido Cinico", if you are sending between each two boards clock and data, what are you using the PLL for?

I mean, e.g. if you have board 1 (B1) and board 2 (B2) and B1 sends data synchronous to the rising edge of the transmitted clock, B2 may read the data in the falling edge of the received clock.

I believe I still don't have in my mind the full picture of your design.

 

[Acido Cinico]

Re: LVDS Signalling

This is how data and clock looks like. You can see that data lines transitions are synchronous to clock in order to minimize noise. So I need a 180deg. delayed, 2x clock inside the FPGA to read data lines.
Hope this helps to figure my system.

So you say that you have a system in which you transmit a 175MHz clock with your data and you have no problems reading your data on the falling edges of the clock?
Please explain your system. What cable type are you using? What connectors? How many layers in your PCBs?

 

[zape]

LVDS Signalling

In my design data was serialized, I was guessing about your solution.

You said, you were thinking about the PLL loosing the lock, did you test the lock signal of the PLLs?

I suppose that internally to the FPGA you are working with the x2 clock, is it correct? How you generate the clock to the next board?

Are you usign Altera FPGAs? Which device? Does it have DDR registers?

 

[Acido Cinico]

Re: LVDS Signalling

I know for sure that the PLL loses its lock since I'm using
the 'locked' output of the PLL megafunction in the FPGA. Each
time PLL loses its lock I force it to re-lock and I can see this
happening from the outputs of each board.
Yes, I'm using the x2 clock for internal operation of the FPGA and
the output clock for the next board is generated by a shift-register
loaded with the incoming clock bitstream.
Yes, I'm using an @ltera Cyclone FPGA. Don't know if I can use DDR
registers since I'm using dedicated LVDS outputs and not DDR dedicated
outputs.
You forgot to tell me how many PCB layers are in your design.
Did you respect the required LVDS track impedances? Tell me about
the cable types you are using.

Thank you very much for your help.

 

[zape]

LVDS Signalling

I believe the problem is not in PCB nor cabling, anyhow:
- PCB: 14 layers, 75ohms.
- Cable: shielded twisted pairs, 100 ohms.

Today I´ll start my holidays, so good luck and keep me informed about your progresses.

 

[kib]

Re: LVDS Signalling

check the jitter in the clock input for ur pll.
if the clock is very jittery then pll may go out of lock

 

[Acido Cinico]

Re: LVDS Signalling

Dear Kib,

I really cannot understand why this clock jitter
appears only at the n-th board if n is greater
than ten. My system is designed so that each
board receives clock and data and then regenerates
new clock and data signals synchronously.
There should be no jitter at all because they
are n, independent, point-to-point connections.
Do you know if A* Cy* FPGAs have an high PLL
sensitivity to power supply noise? Maybe this
is the cause of my loss of lock.

Regards,
A.C.

 

[YUV]

Re: LVDS Signalling

Dear Kib,

I really cannot understand why this clock jitter
appears only at the n-th board if n is greater
than ten. My system is designed so that each
board receives clock and data and then regenerates
new clock and data signals synchronously.
There should be no jitter at all because they
are n, independent, point-to-point connections.
Do you know if A* Cy* FPGAs have an high PLL
sensitivity to power supply noise? Maybe this
is the cause of my loss of lock.

Regards,
A.C.

Hi. Output jitter of each Cyclone FPGA is 500ps. It is not disapperars, it is being accumulated and distorts duty parmeter. But that parameter is very critical for PLL. If you exceed 45...55% duty cycle, PPL will lose a carrier.
Thus, a maximum length of the chain depends on working frequency. A higher frequency will cause a smaller number of devices in the chain.
Also, FPGA output is not the same as in real LVDS chip. Output is required to be compensated. Please, study attached PDF (I don't remember where I have got it).

 

[Acido Cinico]

Re: LVDS Signalling

Dear YUV,

my clock frequency is 45MHz -> 22ns period.
I think a 22ns period can tolerate a 0.5ns jitter.
This 0.5ns interval should be not accumulated
since each board re-generates clock signal.
Infact, the output clock is generated by a state
machine and it is treated exactly as output data.