Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Impedance Matching For Chip Interface !!

Status
Not open for further replies.

suria3

Full Member level 5
Joined
Mar 5, 2004
Messages
300
Helped
17
Reputation
34
Reaction score
5
Trophy points
1,298
Activity points
3,028
Dear People,

I'm doing research on impdeance matching for chip interface. As we know, in order to have have maximum power transfer without any reflection or distortion on the signaL path, the driver and the receiver must match the 50ohms line impedance. There are a few types ofinterfaces available in the market like LVDS, CML,PECL and etc. I have some confusions when come to the impedance matching when use these configuration.

Question:-

I'm attaching a few diagrams of the mentioned interface termination. As we know , in order to match the line impedance, the total output impdeance at the driver is to be 50ohms as well. Is this meant that the load at the output of the stage need to be 50ohms. Let say i have a diff amp as in the diagram, which have a load of 1000ohm, and in the end once i do the ac small signal analysis, i will have the output impedance of 1000ohms with assumption i ignore the large collector-emmitter resistor. So, if this is the case, how can i have the output impedance to be 50 ohms.

If, at the output, i just add 50ohms load to ground in order to match 50ohms line impedance, dont the circuit will look like this 50ohms in parallel with 1000ohms?

I hope, people in this forum will explain to me, how actually the impedance matching is calculated and it is terminated in the right way. Your cooperation is very much appreciated.

Is this 50ohms matching at the receiver and driver is not included the load resistance looking into the circuit itself...please advise.


Thanks in advance,
SURIA3.
 

So, if this is the case, how can i have the output impedance to be 50 ohms.

Use followers so your amp's output impedance is lower.

If, at the output, i just add 50ohms load to ground in order to match 50ohms line impedance, dont the circuit will look like this 50ohms in parallel with 1000ohms?

Yes, but think of your diff amp's outputs as high impedance current sources. Therefore to match to the line, a shunt 50ohm is inserted in parallel with your high impedance current source.
 

So, if this is the case, how can i have the output impedance to be 50 ohms.

In your figure, the ouput impedance of the output buffer will be the 100 ohm due to the collector load resistor. The output buffer, which is a CML type output buffer, is required to have a 100 ohm termination on the output. This result in your 50 ohm impedance looking into the output of the MAX3265, which includes the 100 ohm output termination.

If, at the output, i just add 50ohms load to ground in order to match 50ohms line impedance, dont the circuit will look like this 50ohms in parallel with 1000ohms?.

Yes this is true, but terminating to Vcc is more desireable because the output buffer's VOH=VCC and its VOL=VCC-800mV. The operating voltage of this part is from 3.0 to 5.5V. If VCC=5.5V, and the output is in a VOH state, you will have 5.5V/50 ohms of current (110mA) through your 50 ohm termination resistor if you have it terminated to ground. It's because of minimizing a large termination current that the input termination is tied to VCC versus ground.
 

The primary objective in any impedance matching scheme is to force a load impedance to "look like" the complex conjugate of the source impedance so that maximum power may be transferred to the load for a example let say a load impedance of 2-j6 ohms and the source impedace is 5-j10 and transformed by the impedance matching network to a value of 5+j10 ohms.Therefore the source 'sees a load impedance of 5+j10 ohms , which just happens to be its complex conjugate . It should be noted here that because we are dealing wih reactances , which are fequency dependent , the perfect impedance match can occcur only at once frequency. That is the freqeuency at which the +jX component exactly equals the -jX component and , thus , cancelation or resonance occurs.At all other frequencies removed from the matching center freqeuncy , the impedance match becomes progressively worse and eventually nonexistent. This can be problem in broadband circuit where we would ideally like to provide a perfect match everywhere within the broad passband ..there are methods to do it...........
 

I think source follower is not enough for reduce the resistance
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top