Impedance Characteristic and Pin problem

[OvErFlO]

I want to desing a PCB for a FPGA TQFP144 with a pin width 0.254mm, now for matching my FPGA with my PCB track at 50Ω I need a width track of 0.526mm with a FR-4 with 0.32mm of thickness (distance signal-ground), but this width track isn't compatible with FPGA pin width.
It's absolutely necessary matching Impedance ?
There's another method to reduce width track at 0.254 mm ??? what can I change to reduce it ?

thanks

 

[Uky]

Depends on frequency/speed of interest. If it is really critical, the dielectric thickness should be reduced so that traces can be made thinner. Then you also need to check the resin/fiber ratio as thick fibers could affect Er over distance. (And select board material careful). Most likely however, you could neck down the trace width just as you reach the pads. (And of course, this can be done only if the adjacent pins are used for non-RF/slow speed purposes). That depends on how the I/O was routed in the FPGA...

 

[OvErFlO]

Do you think that 100 Mhz is an High Frequency ?

Added after 25 minutes:

What's my Zo if I don't design a ground plan , but only a dual layer PCB?

 

[jdhar]

Chances are if you are using a 2 layer PCB, you won't have any control over Zo. In order to know Zo, you need to control the height above the GND plane and the know the value of Er. On a 2 layer board, you have no GND plane, and even if you used the bottom side as a solid plane, you probably wouldn't know the Er. And no, 100M isn't a high frequency; you can get away without controlled impedance.