Impact of PLL BW on preformance

[ahmad_abdulghany]

What is the impact of PLL BW on its performance? What's its other trade-offs?

 

[safwatonline]

as far as i can remember : settling time and phase margin and Spurs

 

[jfyan]

as far as i can remember : settling time and phase margin and Spurs

hi,
i don't understand it very well that the bandwidth affect the spurs performance.
so could you state it more clearly?
thanks,
jeff

 

[safwatonline]

when the closed loop BW is smaller the spurs are more attenuated

 

[ahmad_abdulghany]

Do u remember Safwat what let us enlarge BW in case of CDR and decrease in normal freq. synth. PLL?

 

[safwatonline]

all what i can remember is that the CDR BW(phase aquizition) is affected by the jitter spec (Transfer,Generation), also is that the settling time isnot a large function of the BW (as the loop is not changing frequency as in synth.)