Immediate Job Openings for Verilog/SystemVerilog Verification Engineer(s)

Status
Not open for further replies.
S

salam_hr

Newbie level 1
Joined
Jun 25, 2012
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,288
Immediately require Verilog/SystemVerilog Verification Engineer(s) in Bangalore. Experience 2-8 years, Education – Engineering Graduate. Experience in Verilog, and/or SystemVerilog, Experience in UVM, VMM, OVM, RVM or any advanced verification methodology, Experience in verification flows (tools, scripts, flows, waveform viewer), Interested candidates, e-mail resumes to careers@siliconpartner.com

With Thanks & Best Regards
Abdul Salam
HR Operations Executive
Silicon Partner Design Services Pvt Ltd
+91-44-43216781
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…