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im in need of help here

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freakrepublic

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hi ppl, freakrepublic here, please help me with these two problems for gods sake

design a digital lock. assume tow push button switches ,A and B are available that output a single pulse each activation the tow switches are interlocked mechanically so that simultaaneous pulses are not possible the lock shuld have the follwing features :
a-The opening sequnce is AABABA
b-Three B pulses should give an absolute rest.
c-any incorrect use of the Aswithch will cause an out put to ring a bell to warn that the lock is being tampered with


2)
desing the circuit whose block digram is shown in figure 10.p1 (morris mano hardware design) using decoders ,counters,multiplexers,flip flops s-R and so on
the circuit has as input aclock and four select lines
the select lines determine the number by which the input clock
frequecy is divided the output is clock divided by the select
line value if F is the frequncy of the input clock and
D is the binary value of the select lines the output frequency
.F. is f/(D+1).

IF U CAN HELP WITH ANY OF THE PAST TWO PROBLEMS PLEASE DO SO.

Salam
 

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