[SOLVED] Illegal left hand side of continuous assign

[Shyam Joe]

Hi my program is left shifter.
when i'm using i got this error "Illegal left hand side of continuous assign"
following is my coding

---

Code Verilog - [expand]
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module flp(v,u);
input [255:0] u;
output reg [255:0] v;
integer i;
assign v[0]=u[255];
initial begin
for(i=1;i<=255;i=i+1)
begin
v[i]<=u[i-1];
end
end
endmodule

---

Help me to solve dis

 

[dave_59]

See https://go.mentor.com/wire-vs-reg

 

[aruipksni]

Hi my program is left shifter.
when i'm using i got this error "Illegal left hand side of continuous assign"
following is my coding

module flp(v,u);
input [255:0] u;
output reg [255:0] v;
integer i;
assign v[0]=u[255];
initial begin
for(i=1;i<=255;i=i+1)
begin
v<=u[i-1];
end
end
endmodule

Help me to solve dis

you can try :

[syntax=verilog]
module flp(v,u);
input [255:0] u;
output reg [255:0] v;
integer i;

always @ (u)
begin
  v[0]=u[255];
  for(i=1;i<=255;i=i+1)
  begin
    v[i]<=u[i-1];
  end
end

endmodule
[/syntax]

 

[mrflibble]

You cannot do that assign like that:

assign v[0]=u[255];

Why not? Read the link Dave posted.

Instead you can do something like this, either in an initial block or in an always block:

v[0] <= u[255];

 

[Shyam Joe]

you can try :

[syntax=verilog]
module flp(v,u);
input [255:0] u;
output reg [255:0] v;
integer i;

always @ (u)
begin
  v[0]=u[255];
  for(i=1;i<=255;i=i+1)
  begin
    v[i]<=u[i-1];
  end
end

endmodule
[/syntax]

Thanks friend i got d output