Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

ILA using vivado 2013

Status
Not open for further replies.

sreevenkjan

Full Member level 5
Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
1,308
Location
Germany
Visit site
Activity points
3,115
Hey guys,

I am using ILA to observe the output given out by my fpga.However there is an option to write down the data observed into a .csv file by giving the command in tcl.
I had set the sample depth to about 131072 in the ILA so that I could see the data(i.e in my case pixels of an image) transmitted by the fpga and trigger at particular addresses. My image is of size 480x480 1bit depth.However it takes 962 samples to get one row processed in the ILA.so i could capture 136 rows in one trial.

Previously when i captured the data during behavioral simulation it uses about 500 clocks to process 1 row.each clock is of period 10ns.
My question is why does it take 962 samples for each row in ILA and why does it take 500clocks in simulation.Could you tell me the difference between two such processes??
How can i measure the time taken by fpga to process the complete image??..is it the time taken during simulation process??
 

what you mean by i missed something in simulation??what did i miss??...
does the time taken in simulation mean the time taken by my fpga to do the complete process??
 

Ila isn't meant to be simulated, its a debug tool on hardware.

are you sure you've covered realistic cases in simulation? Given there is a misdmatch, something is amiss that you need to find, as we don't have the project.
 

You don't give people much to go on. Try to include more information...
 

yes i used ILA as a debugging tool...in simulation i used a clock fequency of 100MHz..I also set the clk of my processing system to that frequency...when I saw the output obtained from ILA...I got about 962 samples for a row of an image....basically i used ila to see if my fpga is giving the output i need.well its giving the output i need but i do not know how much time it takes to do the complete image.

eg. my input image was 480x480....image data obtained via simulation was 480x480....image data obtained via ILA was 480x962...can you tell me why there is oversampling in the x direction??

How can i check it??
 

With an incorrect image size, there's clearly something wrong. That's about as much help as we can give with the info you've given.

the ila will just capture the data you tell it to. Is there a blank period after a line? Do you have some method of seeing which pixels are on the edge or corners? Start of frame or end of line?

i get the feeling there is a long wait before the next line starts.
 

well I guess i figured out the problem....i am reading a complete row till the last pixel of the row is processed so the row pixel data is being read 2 times by the ILA and that is why i am getting 962 samples which is about two times 480 and i need to use a flag so that it reads only when flag is active..
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top