IF statement doubt in VHDL

[sp]

i have a question to ask on the IF statement in VHDL....

if_statement ::=
IF condition THEN
sequence_of_statements
{ELSIF condition THEN
sequence_of_statements}
[ELSE
sequence_of_statements]
END IF;

above is the BNF statement...

let say we have few more "elsif" statement

IF condition1 THEN
sequence_of_statements1
ELSIF condition2 THEN
sequence_of_statements2
ELSIF condition3 THEN
sequence_of_statements3
ELSIF condition4 THEN
sequence_of_statements4
ELSE
sequence_of_statements5
END IF;

if the first condition (condition1) or either one of the condition is true... will the next few elsif statements condition be checked again? or it will just jump to the end if clause??

i have been read through the LRM but no luck...

thank you

warm regards,
sp

 

[mos_halas]

I think it will jump to the endif whenever any of the conditions is true and is taken.
Mostafa Halas

 

[maksya]

It will jump to END IF after some condition = TRUE. Also, IF-STATEMENT construction produses priority structure. In other words - if more than one conditions = TRUE, only the first in the list will be checked.

P.S.: Use ModelSim to debug code. It allows program stepping.

 

[sp]

i find this in one of my C language ebuk...

********************************************************************

Else-If
The construction

if (expression)
statement
else if (expression)
statement
else if (expression)
statement
else if (expression)
statement
else
statement

occurs so often that it is worth a brief separate discussion. This sequence of if statements is the most general way of writing a multi-way decision. The expressions are evaluated in order; if an expression is true, the statement associated with it is executed, and this terminates the whole chain. As always, the code for each statement is either a single statement, or a group of them in braces.

The last else part handles the "none of the above''or default case where none of the other conditions is satisfied. Sometimes there is no explicit action for the default; in that case the trailing

else
statement

can be omitted, or it may be used for error checking to catch an "impossible'' condition.

********************************************************************

it should b the same for the IF-ELSIF statement in VHDL........(terminates the whole chain when one condition is true)


sp

 

[tkbits]

When synthesizing, there is no jumping.

The sequencing of code represents priority.

So gating is added to give the earlier conditions and assignments priority over later ones.

 

[sp]

When synthesizing, there is no jumping.

The sequencing of code represents priority.

So gating is added to give the earlier conditions and assignments priority over later ones.

however when one condition is true... other will not be selected if they are true after the first "true"??


sp

 

[tkbits]

That is correct.

 

[nee_naresh04]

this is a conditional operator statement...more over VHDL is capable of CUCONCURRENT SIGNAL ASSIGNMENTAND EXECUTION supporting language..as per conditional statement concern ..if the condition is checked and if true corresponding statements executed..so as concern to concurrent signal process..all the statements checked simulteneously....so i think there is no case of jumping...concurrently all r processed but the statements corresponding true conditionalised case only will execute..

 

[Iouri]

Using to many times if/elsif/elsif it is not a good prcatice, better choise will be to use
case construction. look again in your code and try to replace, also consider something like this

a<= b when (condition1) else
c when (condition2) else
............

N when condition N;


Good lack

 

[sp]

this is a conditional operator statement...more over VHDL is capable of CUCONCURRENT SIGNAL ASSIGNMENTAND EXECUTION supporting language..as per conditional statement concern ..if the condition is checked and if true corresponding statements executed..so as concern to concurrent signal process..all the statements checked simulteneously....so i think there is no case of jumping...concurrently all r processed but the statements corresponding true conditionalised case only will execute..

concurrent if it is not in the process... all statement is synthesized but not all are run(hope this word is ok).. when one condition is true, no more is check.... there is a priority encoder...

like wad u mention

concurrently all r processed but the statements corresponding true conditionalised case only will execute

wad if 2 condition is true?...

sp

 

[Iouri]

wad if 2 condition is true?...
Then, which one do you think should executed?
If they have to execude both than there is no reason to have them under the same process or concurent signal assigment, otherwise, introduce third conditions.......


Good lack

 

[sp]

If they have to execude both than there is no reason to have them under the same process or concurent signal assigment, otherwise, introduce third conditions.......


Good lack

hi, no offense, sometimes we might hav few independent condition n some of them might b true... so there is priotrity...e.g:

if (i hav big head) then
statement 1;
elsif (i hav big mouth) then
statement 2;
elsif (i hav bi leg) then
statement 3;
else (do nth);

as we can see, few condition might b true n we only one statement to execute when first true is met(and terminate the whole chain)....so only the elsif statement can do this, using "if if if if" statement will generate wad u think...all true condition will be execute...

sp

 

[Resistance]

hi,
i think if case is true automatically then else is not checked.. so same hols good with elsif too..

regards..

 

[mystique_unbound]

IF statements are generally raelized using parallel architecture like PRIORITY ENCODERS . so obviously if one statement is true the the other statements with lower priority are negkected . the order of priority will follow the structure .
It is similar to that of case statements .

In verilog you can make the if statements resulting in latches but be careful it may lead to race conditions .