If generate statement in vhdl for enabling and disabling hardware

[kalyansrinivas]

Hi

I want to enable or disable logic using en_logic

en_logic is defined as a std_logic input signal from external environment

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Code VHDL - [expand]
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not_gen_logic  :  if (en_logic = '0') generate
 
in1 <=  rx_inp1;
in2 <=  rx_inp2;
in3 <=  rx_inp3;
in4<=   rx_inp4;
 
end generate;

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but strangely i see an error pointed by quartus

"

Error 10807 VHDL error : condition in generation scheme must be a static expression

"

but if i define en_logic as a constant i dont see this error

Please guide me how can we use if generate statement to enable or disable a desired logic

 

[barry]

I think the problem is that the generate statement actually generates physical logic in the FPGA, in other words, it's generated during the compile process, not after it's sitting in the device. You are trying to generate hardware 'after the fact'. You can't do that. You are going to have to rethink your logic. It's not really clear what you are trying to do. If en_logic =0 then you assign a value to a signal, if en_logic=1 you want those signals to cease to exist?

 

[kalyansrinivas]

Thanks for your valuble time

If en_logic =0 then you assign a value to a signal, if en_logic=1 you want those signals to cease to exist?

Sorry i have a logic for when en_logic = 1

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Code VHDL - [expand]
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not_gen_logic : if (en_logic = '0') generate
 
in1 <= rx_inp1;
in2 <= rx_inp2;
in3 <= rx_inp3;
in4<= rx_inp4;
 
end generate;
 
-- input to some filter 
 
gen_logic : if (en_logic = '1') generate
 
inst_filter : filter port map (rx_inp1, rx_inp2, rx_inp3, rx_inp4,out1,out2,out3,out4);
 
in1 <= out1;
in2 <= out2;
in3 <= out3;
in4 <= out4;
 
end generate;

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I expect synthesizer to generate both logic but result is muxed at output

 

[permute]

"generate" only accepts constant/generics for its expressions. It is intended to generate different structures based on the generics provided to an instance of the entity. If you need logic that supports both cases, you will need to write a process that infers a mux. eg, with en_logic in the sensitivity list and with an if-else statement in the process.

The generate is more for cases where you have optional features (eg, a floating point unit might optionally support subnormal values, but not all applications need them). Or for when you have multiple implementations of some feature (eg, a serial adder vs a parallel adder.). Or for when you have different structures based on generics (eg, a 32b read, 16b write ram, a 32b read, 32b write ram, or a 32b read, 72b write ram. each used in cases where the read/write clock is less/equal/greater).

 

[K-J]

Please guide me how can we use if generate statement to enable or disable a desired logic

Look over at the response you received in the Altera forum.

The condition in a generate statement must be static (i.e. constant for a given elaboration). An input signal is not static therefore it can't be used as the condition in a generate statement.

KJ

---------- Post added at 07:34 ---------- Previous post was at 07:29 ----------

Sorry i have a logic for when en_logic = 1

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not_gen_logic : if (en_logic = '0') generate
 
in1 <= rx_inp1;
in2 <= rx_inp2;
in3 <= rx_inp3;
in4<= rx_inp4;
 
end generate;
 
-- input to some filter 
 
gen_logic : if (en_logic = '1') generate
 
inst_filter : filter port map (rx_inp1, rx_inp2, rx_inp3, rx_inp4,out1,out2,out3,out4);
 
in1 <= out1;
in2 <= out2;
in3 <= out3;
in4 <= out4;
 
end generate;

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I expect synthesizer to generate both logic but result is muxed at output

Even if it did generate logic for both, wouldn't you also expect the synthesizer to get rid of the logic generated for 'en_logic = 1'? After all, if en_logic is known to always be '0', then it can never be '1' which means that the logic for 'en_logic=1' will never get executed.

Bottom line, you're using the wrong construct. A process statement is what you need to use, not a generate. It should be a simple few edits to convert your generate into a process. If you have trouble with that, post again.

KJ

 

[barry]

I think you are making this a lot more complicated than it has to be. As said before, what you really want is a mux, something like:

If en_logic='0' then
in1<=rx_inp1;
in2<=rx_inp2;
.....
else
in1<=out1;
in2<=out2;
....
end if;

Won't that do what you want?

Barry