if - case optimization in verilog

[titanic]

Hi, i am wondering which of the following verilog snippet is more efficient in terms of speed and area.

--------CODE 1

reg [4:0] A

if(A[4:0] = 5'b11111)
jobs1
else if(A[3:0] = 4'b1111)
jobs2
else if(A[2:0] = 3'b111)
jobs3
else ifA[1:0] = 2'b11)
jobs4
else if(A[0] = 1'b1)
jobs5


--------- CODE 2

reg [4:0] A

Case (A)
5'b11111 : jobs1
5'b01111 : jobs2
5'b00111 : jobs3
5'b00011 : jobs4
5'b00001 : jobs5

endcase






would eliminating "default" be good or bad for the case statement given above?



Thanx in advance

 

[zhipeng]

They are behaviorally equal. After synthesis, the two will probably become structurally equal too.

Eliminating the default else in CODE 1 or the default: in CODE 2 could be bad for you, if you don't want latches being synthesized for the codes...