eddie vasanth
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hi,
i am getting the following error while i compiling vhdl prog in modelsim.i cant understand what type of error and how to change since i am starter of vhdl..so pls help me out this prob..
here is error i m getting...
1. Identifier "m" is not directly visible.
Potentially visible declarations are:
work.real2bit.m (constant)
work.constants.m (constant)
2.Bad expression in right operand of infix expression "mod".
** Error: F:\Edwin\BPSk project\codings\bps.vhd(37): Bad right hand side (infix expression) in variable assignment.
** Error: F:\Edwin\BPSk project\codings\bps.vhd(43): (vcom-1078) Identifier "m" is not directly visible.
3.Bad expression in left operand of infix expression "-".
** Error: F:\Edwin\BPSk project\codings\bps.vhd(21): Bad expression in right bound of range expression.
** Error: F:\Edwin\BPSk project\codings\bps.vhd(21): Type error in range expression.
** Error: F:\Edwin\BPSk project\codings\bps.vhd(37): (vcom-1078) Identifier "m" is not directly visible.
here it is prog which i need to change
i am getting the following error while i compiling vhdl prog in modelsim.i cant understand what type of error and how to change since i am starter of vhdl..so pls help me out this prob..
here is error i m getting...
1. Identifier "m" is not directly visible.
Potentially visible declarations are:
work.real2bit.m (constant)
work.constants.m (constant)
2.Bad expression in right operand of infix expression "mod".
** Error: F:\Edwin\BPSk project\codings\bps.vhd(37): Bad right hand side (infix expression) in variable assignment.
** Error: F:\Edwin\BPSk project\codings\bps.vhd(43): (vcom-1078) Identifier "m" is not directly visible.
3.Bad expression in left operand of infix expression "-".
** Error: F:\Edwin\BPSk project\codings\bps.vhd(21): Bad expression in right bound of range expression.
** Error: F:\Edwin\BPSk project\codings\bps.vhd(21): Type error in range expression.
** Error: F:\Edwin\BPSk project\codings\bps.vhd(37): (vcom-1078) Identifier "m" is not directly visible.
here it is prog which i need to change
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.constants.all;
use work.real2bit.all;
entity bpsk is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
serial_data : in STD_LOGIC;
clk_data : out STD_LOGIC;
clk_spi : out STD_LOGIC;
clk_bpsk : out STD_LOGIC;
data : out STD_LOGIC_VECTOR (11 downto 0));
end bpsk;
architecture Behavioral of bpsk is
signal pointer : natural range 0 to (M-1) := M-1;
signal value : word := (others => '0');
signal clk_bpsk : std_logic := '0';
begin
process(reset,clk,clk_bpsk)
variable count : natural range 0 to (64*M-1) := 0;
begin
if reset = '1' then
clk_bpsk <= '0';
clk_data <= '0';
count := 0;
elsif clk'event and clk = '1' then
if count = 0 then
clk_bpsk <= '1';
clk_data <= '1';
elsif count mod 64 = 0 then
clk_bpsk <= '1';
else
clk_bpsk <= '0';
clk_data <= '0';
end if;
count := (count + 1) mod (64*M);
end if;
end process;
process(reset,clk_bpsk)
begin
if reset = '1' then
pointer <= M-1;
elsif clk_bpsk'event and clk_bpsk = '1' then
pointer <= (pointer + 1) mod M;
end if;
end process;
clk_spi <= clk;
value <= -table_wave(pointer) when serial_data = '1' else table_wave(pointer);
-- Use the next line for simulation
data <= std_logic_vector(value);
-- Use the next line for synthesis and comment the previous one
--data <= value + conv_signed(2**(nbits-1),nbits);
clk_bpsk <= clk_bpsk;
end Behavioral;
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