Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Ideas for a clamp circuit in LDO

Status
Not open for further replies.
Y

yen

Member level 5
Member level 5
Joined
Apr 21, 2005
Messages
85
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,230
Hi,
Maybe we can use mirror pmos'size and use resistor to transfer the voltage.
Use comparator's output to control pmos's gate voltage. Do you have any simple methods? If you know , please teach me . Thanks.
Do you know line driver of DAC and common mode feedback? If you has any information or data, can you let me know? I want to understand. Thanks.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top