[SOLVED] ideal opamp for integrator

[vaah]

Hello,

I would like to build an ideal integrator in Cadence. Currently, I am using "VCVS" as an amplifier shown in the fig

When I simulate the circuit, apparently, capacitor feedback does not work properly. The opamp model acts like a comparator. As long as negative input has a larger voltage output shows the minimum voltage and Vice versa. I am wondering if someone might have the same problem. I appreciate it if you could let me know how to resolve the issue!

Do you have any suggestion how to model an ideal integrator in Cadence? Preferably, I do not want to use Verilog-A opamp.

Thanks.

 

[crutschow]

Your integrator time constant is only 50nS.
Is that what you wanted?
Try a larger integration capacitor.

 

[vaah]

Your integrator time constant is only 50nS.
Is that what you wanted?
Try a larger integration capacitor.

Thank you
I have tried to use a larger capacitor but I still have the issue.

 

[FvM]

When I simulate the circuit, apparently, capacitor feedback does not work properly. The opamp model acts like a comparator. As long as negative input has a larger voltage output shows the minimum voltage and Vice versa.

That's how an integrator is expected to work. Sounds like you didn't yet think about a reasonable test setup for your integrator.

It can go like this:
Apply an initial condition that holds the integrator capacitor discharged, and watch the output signal starting from this point.

In a real circuit, an integrator would either us a reset switch or external negative feedback.

 

[vaah]

That's how an integrator is expected to work. Sounds like you didn't yet think about a reasonable test setup for your integrator.

It can go like this:
Apply an initial condition that holds the integrator capacitor discharged, and watch the output signal starting from this point.

In a real circuit, an integrator would either us a reset switch or external negative feedback.

Thank you FvM,
Yes you are right! This is how an integrator is expected to work.

I had applied some initial condition to some nodes and also as you can see from the uploaded photo, ive added a resistor in parallel with the capacitor to make sure about the feedback!

What do you mean about a reasonable test setup? Can you please tell me specifically?
Thanks.

 

[LvW]

each opamp suffers from input offset which produces an unwanted dc output. In case of pure capacitive feedback this dc voltage causes an unwanted charging of the capacitor.
Hence, dc (resistive) feedback is required in form of a resistor parallel to the feedback capacitor.
However, this resistor disturbs the integration.
As a consequence a trade-off is necessary (as very often ikn analog electronics):
The feedback resistor should be as large as possible (regarding its influence on the integration process) and as small as necessary (with regard to its dc stabilization task).

 

[vaah]

each opamp suffers from input offset which produces an unwanted dc output. In case of pure capacitive feedback this dc voltage causes an unwanted charging of the capacitor.
Hence, dc (resistive) feedback is required in form of a resistor parallel to the feedback capacitor.
However, this resistor disturbs the integration.
As a consequence a trade-off is necessary (as very often ikn analog electronics):
The feedback resistor should be as large as possible (regarding its influence on the integration process) and as small as necessary (with regard to its dc stabilization task).

Thank you

exactly! But I have applied a saw waveform and also applied initial condition. Theoritacclly, i think the circuit shold work, shouln't it?

 

[FvM]

You didn't show any waveforms so we can't know if your test setup is correct.

 

[vaah]

You didn't show any waveforms so we can't know if your test setup is correct.

Right, please take a look at the photo.


the amplifier has 4 pin, Vi+ Vi- Out and (Vg connected to ground). I have applied a DC voltage to Vi+ and I have a negative feedback for the amplifier. The problem is, as I told earlier, the capacitive feedback doesn't work, however I put a large resistor in parallel with the capacitor.

I have also tried to make a switched-cap with an ideal amplifier. See the photo. I assumed that the amplifier works properly. But unfortunately, I have more problem with this circuit.

 

[D.A.(Tony)Stewart]

10 pF Cap will integrate and saturate in microseconds. Remember dv/dt=I/C so with C=1e-11 the slewrate is far too fast.
Try 1 nF. or calculate what you need.

 

[vaah]

10 pF Cap will integrate and saturate in microseconds. Remember dv/dt=I/C so with C=1e-11 the slewrate is far too fast.
Try 1 nF. or calculate what you need.

Thank you.
You are right I should consider the charge and discharge timing. I am using a triangle and saw waveform. So incited of using large value for capacitor, I change the frequency of input.

BTW, it seems my circuit works. If it helps to others:
I couldn't simulate an integrator. However, when I added some switches to the circuit it works. The other problem for "vsvs", a component in analogLib" was "time delay".

Also, be careful for your simulation setting, specifically, "gmin". dont float a node, put a large resistor!

Thank you all!