[SOLVED] Idea for Address-Decoder Design (AHB-Lite system)

[dpaul]

Purpose: Need idea on AHB-Lite Address-decoder

Background:
I am implementing an AHB-Lite system & have gone through the AMBA spec.

I have 6 slaves (inc. the default slave).
So I must have HSEL_S0 to HSEL_S5 generated by the Decoder.

The address space for the slaves have already been decided.
e.g.- Slave0 has 0000 0000 to 0000 03FF,
Slave1 has 0000 1000 to 0000 1FFF ,
Slave2 has 0000 3000 to 0000 33FF, etc.

So when the HADDR sends data, we know for which slave it is meant for!

Now the input to the decoder is the 32 bit address bus (HADDR).


So I need an idea as to how shall I design this decoder?

My idea - Write Verilog code something like this:

if (Address is between 0000 0000 to 0000 03FF)
HSEL_s0 <= 1'b1;
HSEL_sX <= 1'b0;(all other HSEL)
else if (Slave1 is between 0000 1000 to 0000 1FFF)
HSEL_s1 <= 1'b1;
HSEL_sX <= 1'b0;(all other HSEL)...and so on!!

Is this the correct approache?

Or is there a better way to do it?

Thanks in advance,
DP

 

[Iamventure]

Hi this is more of a behavioral code or code for a test bench.
The best way to design is to assign each of the HSEL bit to the function based on address on clock edge or continually.
i.e.
assign addr_space = (Address (31:15) == 0);
assign addr_nib3_eq_3 = ~Address (11) & ~Address (10) & Address (9) & Address (8);
assign HSEL_0 = addr_space & ~Address (14) & ~Address (13) & ~Address (12) & addr_nib3_eq_3;
assign HSEL_1 = addr_space & ~Address (14) & ~Address (13) & Address (12);
assign HSEL_2 = addr_space & ~Address (14) & Address (13) & Address (12) & addr_nib3_eq_3;

If you give the complete set of address, its possible to optimize the decoding logic.