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Iddq testing & pattern generation in DFT(Design For testability)

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shalin mandiwala

Junior Member level 3
Jun 15, 2015
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Hello all.

In which case i compulsory need to use Iddq testing and not stuck-at fault test.?
Please give me any example.

Also want to know how we observe Iddq strobes inserted by TETRAMAX tool for each pattern.
I mean we need to observe a single pin for Iddq from top? I am very confused.

Thanks & Regards.

Consider the below circuit:

stuck at fault.PNG

From it you can see two stuck fault at two different point.

Here we will conclude that their is no pattern which can detect both the fault at a time.

And while applying test pattern for any one fault will give the expected output and not the faulty output. So the consider fault is undetectable. This effect is called fault masking, where one fault in the circuit will mask the other fault.

This generally occur in circuit as above where redundant logic is present. To detect such undetectable fault we need to go for Iddq fault modeling where you can apply node with high or low voltage and due to stuck fault their will be significant increase in current.

I hope you got it.
Thank you for your reply. It clears my doubt.

Now,Just want to know practically how we measure Iddq current? I mean from top module itself? There should be some rules.

During the IDDQ, the tester need to measure the current on the power pads of the design which supply your digital.
The stop point indicated by the tool is when you should measure the current.

So, the power pads are top-level pins which supplies the digital ??

My question is how would you measure current at one particular node by measuring top-level power-pads? If you have any example then it would be more clear.

I am not getting the picture.

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