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[SOLVED] ICCOMPILER : Problem with locking

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antar507

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Hi,

I'm working on place and route of a design in Synopsys IC Compiler.
I have gate netlist from DC Compiler and I'm getting the following error while running "read_verilog" in ICC.

***** Verilog HDL translation completed! *****
Elapsed = 0:00:00, CPU = 0:00:00
Hierarchy Preservation is turned ON
The quick-attach skip-search mode has been turned on.
WARNING : Could not create cell lock file, giving up. Pleae check the link command
Elapsed = 0:00:05, CPU = 0:00:00
0

I'm using Synopsys SAED 90nm library and here are the commands which I'm using


set search_path "."
lappend search_path "../files/Digital_Standard_cell_Library/synopsys/models"
set link_library "* saed90nm_max.db saed90nm_min.db saed90nm_typ.db"
set target_library "saed90nm_max.db"
create_mw_lib -technology ../files/Digital_Standard_cell_Library/process/astro/tech/astroTechFile.tf \
-bus_naming_style {[%d]} \
-mw_reference_library ../files/Digital_Standard_cell_Library/process/astro/fram/saed90nm_fr \
DES10

open_mw_lib DES10
read_verilog -top DES10 DES10.v

I'm still a newbie at IC compiler and I'm not sure if I'm setting up Milkyway Libraries right.
Please do let me know if I'm not clear or you need more info.

Any help would be highly appreciated.

Thanks
Antar
 

It was some issue with my workstation and nothing related to IC compiler. Resolved !
Thanks Anyways who looked at it.
 

Hi.
I have same problem above that!
and I know it is related to my workstation.
But.. I can't solve it because I can not figure out which point is wrong...
Please let me know how did you solve it.
Thank you.
 

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