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IC Layout:- Running LVS

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20tech11

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Hi All,

I have a basic doubt may be it is stupid. I am working with the design of a 8 bit DAC and for better matching I have to follow common centroid geometry and have to add dummy elements. But when we run LVS will these dummy elements be considered as extra instances and Will the LVS show more instances in the Layout when compared to the original schematics.This means my original schematics and extracted schematics do not match at all.So how can I pass my LVS?

Thanks guys
 

ira2008

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you add dummy cells in your layout, so you must put the same dummy cells in your matching schematic.
 
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