Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] IC compiler

Status
Not open for further replies.

Stirgamight

Newbie
Joined
Aug 14, 2020
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
48
ICC
I keep running into that error no matter how small the ring width is (I made it 0.8)


Error: The die size is too small to synthesize any power plan
(PNA-099)
Please specify smaller ring width
 

Attachments

  • pnr.txt
    3.8 KB · Views: 81

What is the die size? May it be really too small to implement any ring width?
 

How can I know that?
Is there a command to report it? or it is just the area of the core?
 

Units = ???

Like, an 0.8um power ring dimension is not
likely to encompass more than a single
180nm FET or a handful of finFETs.

0.8cm, now you've got a chip scale bus ring.
 

do you have an empty core? trying to draw anything around it causes errors.
 

That was actually solved by either not mentioning the ring width at all in the command (I am not sure what the result is) or by redefining the die area with the "estimate_fp_area" command, thanks for the replies
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top