[SOLVED] IC Compiler & Macro Pin Min Area Problem

[zxvc]

IC Compiler & SRAM/Macro Pin Min Area Problem

I have a design with SRAMs (macros).
Each logical pin of the SRAM has three physical pins (draw by metal1-3.)
I use IC Compiler for APR my design.

Unfortunately, after routing, the min area DRC errors are generated at locations of SRAM pins.
The problem comes from:
IC Compiler doesn't use all pins of SRAMs for connections but only one of three physical pins of each logical pin.
Thus, the unused physical pins violate the min area errors.

How do I solve this problem?

 

[rca]

1-For some router you could request to connect all metals of a pin. It is necessary when we know there is no internal (inside the cell/macro) connection between all this metal of the same pins.
2-some router have variable to fix automatically this king of issue by added metal, no necessary enable by default.
3- in last case you need to script this to fix them (I already did it with an older Magma blast version)

 

[zxvc]

Hi rca,

I had tried any possible IC Compiler (2010.03) Zroute option, including "set_route_zrt_detail_options -check_pin_min_area_min_length true -check_port_min_area_min_length true," unfortunately, no one has the effect.
The solution 1 and 2 would be the better solutions if they were to be available.

I hadn't consider the solution 3 before. I think it is possible and will try it.
Thanks for your suggestions.

However, I still hope someone could tell me the solution 1 or 2 for IC Compiler, if they were to be available.

 

[rca]

Did you asked to the support? In general, you are not alone in this case.

 

[oratie]

I think you can ignore it now. Later, when you will write out the GDS file, and run DRC (Calibre or Hercules), these violations will disapper. You see them in PnR (ICC) tool, because it works with some kind of abstract view (FRAM for ICC). In this abstract the pins are just a small portion of metal. But, in the real layout of macro block (CEL view or GDS), these pins are bigger, they have long metal wires, connected inside. So, when you run DRC on the complete layout, you will not see min area violations (because, macros provider check their product with DRC tool and fixx any errors before selling them to you). It's a usual case.

Still, some macros may have real min area violations - in this case, it should be mentioned in macros app. notes (or datasheet).

 

[zxvc]

Hi rca,

Thanks for your suggestion again.
I have sent a mail to the technical supporters (though they are not Synopsys technical supporters) and am waiting for their reply.

Hi oratie,

I also agree with your word that some information of macros could be hidden and generate some false DRC errors,
because I certainly met a similar problem before.
Unfortunately, I have no the real layout of those SRAM macros and can't confirm the min area problem can be solved on the complete layout by myself.
I will discuss this possibility with the technical supporters.
Thanks for your information.

 

[zxvc]

Hi rca and oratie,

My technical supporter has replied me. He confirmed this min area problem came from the incomplete layout.
After replacing the macros with their real layouts, the min area problem will disappear.

Thanks for your suggestions.