I2C IP validation in FPGA

[s_barani]

validation i2c

Dear Experts,

I have a functionally verified I2C core for which i have to do validation in an fpga development board which has Cyclone II fpga.
There are no other I2c devices in that board to communicate with the FPGA. I dont have other verification IPs too .
My question is Can I use Two instantiations of the IP core , configure one as master and the other as slave and loopback them thro IO pins to perform validation of the core.

Also please let me know some general guidelines for doing IP validation in FPGA.

 

[kvingle]

Yes you can do that.

You can write a top level container in HDL which instantiates and interconnects one master and one slave I2C devices.
For testing you can write a small memory as I2C slave.
master can write and read back to check communication.