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I want to design MOSFET layout in cadence

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I want to design MOSFET layout in cadence, how can I start?
 


When you say "design" do you mean simply demonstrate,
or optimize to the foundry's capability and the application
you anticipate? Anybody can make a poly rectangle cross
a thin-oxide cut and lay N+ or P+ over it and sink a
contact on both ends. This is the trivial part. Modern
MOS devices have much subsurface detail which has
to do with both mask layers (sometimes Boolean and not
seen by the designer) and process (angled implants, hard
masking spacers, etc.).

So just what do you think you're "designing" here?
 

Thanks for replay , actually I am not getting Virtuoso Layout Editor in my cadence

- - - Updated - - -

I am using 16.3 version
 

Thinking twice, I guess you thought of . It should include the layout software ... if you have access to the corresponding license.
 

I have candence 16.3 it is possible to design IC in it?
 

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