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I used asynchronous reset in my design, and now found...

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sunms

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I used asynchronous reset in my design, and now found in the test that the chip doesn't work stable.

Because the chip is about 5 million gates,so I don't apply synchronous reset in my design.

But now in the system test,there's need that I have to reset the datastream connecting to another chip. And the chip's output will be in chaos.

So can anyone tell me how to avoid this in the future design. Only refer to synchronous reset is also not a good way,for it will include many additionl logics.
 

eda_wiz

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Synchronise the external asynchrous reset with a Synchroniser circuit. Also you may use Asynchrous assert synchronous deassert methodology.

"Only refer to synchronous reset is also not a good way,for it will include many additionl logics."

Actually synchrnous Reset Flipflop consumes less area than asynchrnous reset FFs. checkout your library datasheet

regards
 

jarodz

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Is the synchronous reset FF that you mean FF without reset pin?
As I know, synchronous reset FF is consisted of a FF without reset pin and a mux.
Therefore the area of synch reset FF is larger than async reset FF.

In a design, some of FFs can be without reset.

Regards,
Jarod
 

quake

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whizkid is right. Can this problem be sovled by using
both sync and asyn reset for different parts? In real
implementation is this ok? and in what kind of part should use sync and in what kind of circumstance
should usd async in realized design?
thanks.
 

eda_wiz

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jarodz said:
Is the synchronous reset FF that you mean FF without reset pin?
As I know, synchronous reset FF is consisted of a FF without reset pin and a mux.
Therefore the area of synch reset FF is larger than async reset FF.

In a design, some of FFs can be without reset.

Regards,
Jarod

IF you check out the gate level circuit of a flip flop....
To make a synchronous reset from a DFF with no reset ,only one AND gate is required. But for an asynchrnous reset flop the circuit requires 2 AND gates.

Also, I talked about a Integrated synchrnous reset FF std cell, not a seperate AND gate/MUX and DFF.

You can check in Any Std cell library...
 

kctang

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Another way you can think of is to use a Schmitt-trigger input pad with pullup (active-low reset, 5~10kohm). This can reduce the chance that board-level noise injected into reset pin.
 

sandusty

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For a chip of such size (5M gates), using an uncontrolable reset signal, you are generating a big hole for DFT.

Have you every thought of the mass-production issues?
 

quake

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hi, sandusty
could you please explain it more?
 

sandusty

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For the DFT issues, please keep the async. reset for all the flops. However, you would like to use sync ckts at the very input point to re-sync the async. reset-singal from another chip.

Currently the scan-insertion tools can fix the sync reset problem by gating the reset signal generated in the chip. But for the safity reason, we would like to keep all the flops reset in the async method.
 

william_qiu

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sandusty said:
For the DFT issues, please keep the async. reset for all the flops. However, you would like to use sync ckts at the very input point to re-sync the async. reset-singal from another chip.

Currently the scan-insertion tools can fix the sync reset problem by gating the reset signal generated in the chip. But for the safity reason, we would like to keep all the flops reset in the async method.

Do you mean the re-sync circuit can't be covered by DFT?
 

wangkl

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I think its not a simple reset issue in gate-level.

When there're two or more chip in your system, u'd better to consider more cases.
Will these chips assert reset and release at the same time?
Could it be pemitted that one chip could be resetted while another chip is still running?
Is there any physical layer protocol/handshake between two chips?
Does the reset value and reset statemachine be correct and make the interface signals not violate the protocol/handshake?
 

mic_huhu

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I think it must be handled at RTL code.
 

jjww110

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i think synchronous reset is a better way
 

wkong_zhu

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synchronous reset has a problem that, it can work when there is no clock, so if you want to reset the chip before PLL provides clock, you must use asynchronous reset.
POR is asynchronous reset.
 

lionchen

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common asyn design problem u met.
most text books offers examples, and u can refer to deepchip for the async reset discussion, good luck
 

Kulprashant

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hi,
you can use synchroniser circuit or handshake procedure.

with regards,
kul.
 

vivek

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jarodz said:
Is the synchronous reset FF that you mean FF without reset pin?
As I know, synchronous reset FF is consisted of a FF without reset pin and a mux.
Therefore the area of synch reset FF is larger than async reset FF.

Hi jarodz,
Can you please explain the synchronous reset flip flop as you have described?
it will be good if you can draw and show it. Is this how a synchronous reset FF realised after synthesis?
 

darylz

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can you explain more on what difficulty you meet?
 

power-twq

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you can try following method (search pdf from google), it's very smart.

CummingsSNUG2003Boston_Resets.pdf

sunms said:
I used asynchronous reset in my design, and now found in the test that the chip doesn't work stable.

Because the chip is about 5 million gates,so I don't apply synchronous reset in my design.

But now in the system test,there's need that I have to reset the datastream connecting to another chip. And the chip's output will be in chaos.

So can anyone tell me how to avoid this in the future design. Only refer to synchronous reset is also not a good way,for it will include many additionl logics.
 

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