# I/S/E5.1 error: can include constants.v

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#### hqqh

##### Full Member level 4
I/S/E5.1 problem

hello,

i'm using I/s/e5.1 to synthesize my verilog code. but every time there is an error message: "can't include constants.v".
This is an verilog file, that should be included in the file top.v.
I really dont know, where the problem is.

#### leonqin

##### Full Member level 4
try to remove the constants.v from projetc

#### Nobody

##### Full Member level 3
you can use C style header .
ifdef CONSTANT
<leave here empty >
else

define CONSTANT
.
.
.
endif

#### it_boy

##### Full Member level 3
This can even be a problem with the path of the constants.v file. If you have the source files in a saperate folder than the xilinx project directory, try put the constant.v file in the project directory.

#### maestor

##### Full Member level 3
Hi,

I am not very used to synthesize with I/S/E but I think, and correct me if I am wrong, that when you create a project and add your source files *.v or *.vhd then asks you if the file is either a package or a module or ... I guess you have added your packages properly. Are they at the top of the list?
If so as soon as you add the top module you should get question marks in components which are instantiated and not added yet. If you add the 'constants.v' then the question mark in that file will dissapear.
'constants.v' sounds like a package, if so add it like a package (at the top) and I would advise you to change the naming in your files and use something like pkg_<name_ design>.v for them.
Then synthesize it (maybe this is what you were doing)

Did you compile your files before you synthesized them? Maybe is a compilation error, M@delsim is the tool you need, if you don't have it there is a free version (slow like hell) that you can download from their site.

I hope it helps, good luck,
Maestor

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