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In 5.1i there is no support for Spartan XL and XC4000 series
of xilinx FPGA. Also 5.1i uses xilinx's own synthesis tool while
4.1i uses synopys FPGA Express.
I guess there are some improvements in supporting newer devices.
The fundametal difference is in using the Virtex-II pro device.
It has the IBM powerpc core in it.
EDK (embedded development kit) can be used under ISE5.1i sp1 or sp2.
I think the major change from ISE 4.2 to ISE 5 is it's place and route engine. The place and route engine is now much more powerfull than before. I Implemented a big 6 million gates design with both of ISE 4 and 5. In ISE 4, I could gain better clock frequencies when I set some additional area constraints. ( Some area constraints in addition to what you set for your modules. ) However in ISE 5 I could never obtain better clock frequencies using this technique.
This means that the place and route engine is doing it's work very very well.
Additionally , There is now a new tool PACE in ise 5, which lets you to do the pin assignment process much more efficiently. Using floorplanner you have difficulties doing pin assignment, specially when using I/O signalings other than normal LVTTL, such as SSTL or ...
The area constraints can now have shapes other than a simple rectangle.
I think there is much much more, and It is really a good idea to switch to new ISE.
hi
in ise 5.1 is missing FPGA express as vhdl or verilog compiler.
in this pachet xilinx use our proprietary compiler.
Xilinx says also that this is better for fitting .
Bye
G
Note one more difference. ISE4.2i for windows works on all platforms like windows 98/NT/2000. ISE5.1i does not work on windows 98 but works on windows 2000!
I have not tested on windows XP.
i think no if you buy the ise as alliance and not as foundation.
in case of alliance i think that you can use as you like.
In every case i prefer use the ise as foundation.
I think the major change from ISE 4.2 to ISE 5 is it's place and route engine. The place and route engine is now much more powerfull than before. I Implemented a big 6 million gates design with both of ISE 4 and 5. In ISE 4, I could gain better clock frequencies when I set some additional area constraints. ( Some area constraints in addition to what you set for your modules. ) However in ISE 5 I could never obtain better clock frequencies using this technique.
This means that the place and route engine is doing it's work very very well.
...
Not necessarily. Did you get higher clock frequencies in 5.1 than in 4.1 with floorplanning ? Can you post some statistics on speed/area in 4.1 and 5.1 ?
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