Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

I/Os Voltage values and delays in any FPGA

Status
Not open for further replies.
B

Bustigo

Member level 2
Joined
May 7, 2011
Messages
53
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,588
What is the relation between (Vdd) I/Os Voltage values and delays in any FPGA, Is that increase Delays ? Why?
and How i choose the best I/Os of FPGAs to optmize delays ??
 

Status
Not open for further replies.

Similar threads

S
Inffering logic delays in an asynchronous FPGA design
Replies
10
Views
1K
xtcx
X
S
Data into a FPGA - define Values of '0' and '1' in into FPGA
Replies
4
Views
2K
shitansh
shitansh
verylsi
[SOLVED] SelectIO in FPGA and output source voltage in FPGA
Replies
6
Views
1K
verylsi
verylsi
A
Input and output delay values for FPGA
Replies
1
Views
522
Akanimo
A
M
FPGA UART Receiving - how do I read and assign values
Replies
4
Views
4K
maheshkuruganti
M

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top