I only have 61.44Mhz clock, how can I get 2Hz and 20Hz clock

[yerics]

I only have 61.44Mhz clock, how can I get 2Hz and 20Hz clock efficiently

thanks

 

[eltonjohn]

Re: I only have 61.44Mhz clock, how can I get 2Hz and 20Hz c

you will never get that clock "efficiently" from that freq.

You are better off designing a low freqency clock .Perhaps from a 32khz watch oscillator and dividing it to get what you want ..
If the power line in your country is 60 hz well then you could use it with a small isolation transformer an then clip the signal an order to square it
and divide it by 3 to get your 20Hz and by 30 to get your 2 Hz ..!

 

[cretu]

Re: I only have 61.44Mhz clock, how can I get 2Hz and 20Hz c

from my previous experience...it's better to keep the clock division less then 1/64..max 1/128. And before I forget...if you do an asynchronous division you add jitter(cycle-to-cycle)..so it's better to use synchronous dividers. Check the web, you'll be able to get some useful articles

 

[brmadhukar]

Re: I only have 61.44Mhz clock, how can I get 2Hz and 20Hz c

Yes you can use the above method if you are not concerned with timing and is probably the "best" way to do. You require a 27 bit counter if you use dividing principle. You may use times in processors to generate a smaller frequency and playaround it.
The SPORT of a DSP may be efficiently used for this purpose but this is not an economical way to do.

 

[homeadd]

do you want to use FPGA?

 

[yerics]

Re: I only have 61.44Mhz clock, how can I get 2Hz and 20Hz c

thanks for all your answers .

I just use it in FPGA,
61.44MHz is my system clock
and I need to control one LED, it's winking frequency is 2 HZ when normal, 20Hz when abnormal

I think perhaps I have to use a 22 bit counter, although it needs some area.

thanks for your help all.

 

[maestor]

Re: I only have 61.44Mhz clock, how can I get 2Hz and 20Hz c

A 22-bit counter, some area... 8O

What FPGA do you want to use or are you using? because you can fit tons of 22-bit counters in today's FPGAs...

--maestor

 

[verilogsh]

Re: I only have 61.44Mhz clock, how can I get 2Hz and 20Hz c

The simplest way i see:
1) divide the system clock by 16 with ICS542 **broken link removed**. U will receive 3.84MHz clock.
2) Apply this signal as a system clock to some uC. For example MSP430F1101 ($1.2) http://focus.ti.com/docs/prod/folders/print/msp430f1101.html . Using the internal timer u can easy divide this clock by any factor u need. All tools for this uC are freeware and very simple to use.
Conclusion: u need 2 small and cheap ICs.

 

[tlp71@hotmail.com]

Re: I only have 61.44Mhz clock, how can I get 2Hz and 20Hz c

another way is to divide inside fpga your system clock, you may have glitch for the big divider, you can solve this problem reclocking the divided clock whit th master clock, so if you have a precise divisor there is no problem, instead you can use a external pll, as cypress, the cy22xxx family have a big number of bits to divide and multiply.
Bye.
G.

 

[ASIC]

PLLs and stuff.... it sounds really expensive. I would go for the FPGA approach.

One question for cretu. Why is it better to keep the division ratio to 1/64 or 1/128 the most?


ASIC

 

[ZeleC]

i dont think that cretu was talking about FPGA, i dont think that would be a problem in using FPGAs Im seeing codes that divide the clock from 4MHz to 2Hz .
So i think that u should use a counter and i dont think it will take place u can even emplement a 22 bits counter in a small CPLD.

 

[cretu]

PLLs and stuff.... it sounds really expensive. I would go for the FPGA approach.

One question for cretu. Why is it better to keep the division ratio to 1/64 or 1/128 the most?


ASIC

If you are using a PLL with a divison ratio >128 , what I've seen in IC design , you'll get a poor clock jitter performance for your clock and/or problems with the speed of locking.