I Need Your Guidance in FPGA !

[Kynix]

Hello~everyone

I’m a beginner in the FPGA. The past days I have learned the language of Verilog HDL and digital circuit. I have changed the following code and I am get into hot water. The conclusion is about the usage of Parameter and assign. In the process of learning Verilog,I haven’t seen the usage of some keywords while they are just understood by some examples. As a result, the problems come up when using. Anybody can teach me ? I will resign myself to your guidance.

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Code Verilog - [expand]
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module test_Change1 (A, B, C, L);
 
input A, B, C;
 
output L;
 
reg a = 1'b1, b = 1'b1, c = 1'b1;
 
//assign a = 1'b1;
//assign b = 1'b1;
//assign c = 1'b1;
 
//parameter a, b, c;
 
always @(posedge A)
* * * * a = 1'b0;
always @(posedge B)
* * * * b = 1'b0;
always @(posedge C)
* * * * c = 1'b0;
 
assign L = (a&b)|(a&c)|(b&c);
endmodule

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Your help will be appreciated！Thanks a lot.

 

[dpaul]

If you've somethings declared as a reg, then you have to give it values inside a procedure ( always or initial blocks ).

I don't seen any clock in your design so a = 1'b0; looks ok to me. But where are your begin ..... end for the always blocks?

The output signal L, defaults to wire output type so assign L = (a&b)|(a&c)|(b&c); is also ok.

What is the problem you are facing? What does your compiler say?

 

[FvM]

But where are your begin ..... end for the always blocks?

No problem to have a single statement after always@().

The design has multiple drivers for a,b and c when using assign. If useful at all, the regs can be legally preset in an initial block. The construct translates to a power-on preset, if available in the respective FPGA hardware. The initializer expressions in the reg definition may be already recognized as power-on preset.

Better to provide an asynchronous preset signal to the always blocks.

Besides fixing semantic/syntax errors, what's the purpose of the design?

- - - Updated - - -

It makes no difference in this case, but you should generally use non-blocking "<=" assignments for register logic.

 

[vGoodtimes]

I'm not entirely certain this is intended to infer registers. I suspect the assigns were intended to be initial -- at least for a first sim. After which there would be more questions.