[SOLVED] I need to write a verilog code to generate a signal which goes high for one clock pulse after every tenth clock pulse

[tipra]

I need to write verilog code wherein I need a signal which goes high for one clock pulse after every tenth clock pulse. I tried something this way,

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Code Verilog - [expand]
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module top  #(
                  WIDTH=8
                 )
                 (
                  input clk,
                  output reg [WIDTH-1:0] sig1,
        
                  );
     reg [WIDTH-1:0] count;
     always@(posedge clk)
     begin
      count <= count + 1;
      if (count == 'd10 || count == 'd20 || count == 'd30 || count == 'd40 )
       begin
         sig1<= 1;
       else
         begin
          sig1<= 0;
         end
    endmodule

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This code works fine and is able to produce the required signal 'sig1' which goes high for one cycle after every tenth clock cycle.

Is there any better and generalized way to generate 'sig1' with the required characterstics?

Note: I intend to use this signal 'sig1' in a larger design which needs to be synthesised.

 

[KlausST]

Hi,

try this:
**********
...

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Code Verilog - [expand]
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begin
     count <= count + 1;
     if (count == 'd10 )
      begin
        sig1<= 1;
        count<= 0;
      else

---

...
*************
width could be "4"

Klaus

 

[ads-ee]

KlausSt your code example results in a divide by 11 pulse generator not a divide by 10 as it resets to 0, so 0-10, 0-10, ....

The original code only produces 4 pulses then has a gap of 225 (give or take a clock) clocks before the next pulse, so it doesn't work correctly either.

A divide by 10 pulse generator can be done similar to this code.

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Code Verilog - [expand]
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always @(posedge clk) begin
  if (rst) begin
    count <= 'b0;
  end else if (count < DIVIDE_BY_N-1) begin // for 10 uses count < 9
    count <= count + 1;
  end else begin
    count <= 'b0;
  end
end
// combonational pulse output
assign sig1 = (count == DIVIDE_BY_N-1) ? 1'b1 : 1'b0;
// or synchronous pulse output
always @(posedge clk) sig1 <= (count == DIVIDE_BY_N-1) ? 1'b1 : 1'b0;

---

 

[KlausST]

Hi,

KlausSt your code example results in a divide by 11 pulse generator not a divide by 10

I'm in need of an excuse..
O.K. here it is: the OP says: " one clock pulse after every tenth clock pulse"
.. after the tenth is the eleventh ;-)

No, joke aside. For sure you are right. It counts 0 .. 10, but should 0..9

Klaus