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I need one help in my project please help me

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sinjani

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I am an M.Tech Student doing Project in Data Aquisition system design..I got a code from one institute but when am compiling it in ModelSim am geting an error "failed to acess A54SXA which is an actel library file , but in my college we are using XIlinx .. I am unable to solve this problem.. could anyone please help me ... I have a seminar on tuesday but my project is incomplete with this error :( . Please help me in this issue .
 

chipseller

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Hi

If this is Behavioural code then delete the library and use definitions of the Actel part. If it is an Actel HDL netlist, then you will need to convert the components in the Actel library to Xilinx equivalents, which could take forever.

If you post your code I can tell you exactly what you need to do
 

sinjani

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Hi thanx for the reply

ok i wil post the code please help me out

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY A54SXA;
USE A54SXA.ALL;

ENTITY SCM_TOP_MODULE IS
PORT(


MC_RST : IN STD_LOGIC; -- COMING FROM MICRO CONTROLLER
BITCLK : IN STD_LOGIC; -- BITCLK FROM MICRO CONTROLLER
SYNC_FRAME : IN STD_LOGIC; -- COMING FROM MICRO CONTROLLER
SER_MC_DATA : IN STD_LOGIC; -- PROGRAMMABLE DATA FROM MICRO CONTROLLER



DAC_SER_DATA : OUT STD_LOGIC;
DAC_CLK : OUT STD_LOGIC;
DAC_SYNC : OUT STD_LOGIC;

ADDRESS : IN STD_LOGIC_VECTOR(4 DOWNTO 0);

SWITCH_ENABLES : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

AMP_SER_DATA : OUT STD_LOGIC;

ADC_CLK : OUT STD_LOGIC;
ADC_SOC : OUT STD_LOGIC;
ADC_SER_DATA : IN STD_LOGIC;

SCM_SER_OUT : OUT STD_LOGIC;

TEST_ADC_CLK_CNTR : OUT STD_LOGIC





);

END SCM_TOP_MODULE;
 
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chipseller

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Hi Sinjani.

This VHDL file links together four sub-components:

ADC_INTERFACE, PROG_DATA_DECODE and PROG_DATA_LATCH are all going to be additional VHDL files. I may need to see them.

CLKINT is an ACTEL specific library macro which is used to promote an internal logic signal (rather than an input pin) to a global or clock distribution network. I do not know if there is a Xilinx equivalent, but you may not need one as the Xilinx tool should be capable of auto-promotion of nets. If not it will be possible to input some form of constraint to force it (I have not used Xilinx for a long time)

If we assume that the first three components do not use any Actel specific components then:

Delete the two lines

LIBRARY A54SXA;
USE A54SXA.ALL;

delete the following:
COMPONENT CLKINT
PORT (
A : IN STD_ULOGIC;
Y : OUT STD_ULOGIC);
END COMPONENT;

As I cannot see all the file I will have to generalise a bit but further down you will see something similar to this:

U4: CLKINT
PORT MAP(
A => Input_Signal,
Y => Output_Signal);

Delete or comment out the above and replace it with:

Output_Signal <= Input_signal; (using the real signal names of course)

We can worry about the function of the CLKINT later. As I said, you probably don't need it anyway

If any of the other three modules have the lines:

LIBRARY A54SXA;
USE A54SXA.ALL;

just delete them.

That should be it, Modelsim should be happy.
 

yanzixuan

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you must add ACTEL library in you design and do this again. But if you are using Xilinx, you need re-compile your RTL level codes by using ISE.
 

sinjani

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Hey thanx for the reply since i cant post my code completely here ..can u please provide me the email id so that i can mail.. please help me out in this issue...
 

chipseller

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Hi Sinjani
Try what I have already suggested above first. That should work. If it doesn't, then either reply on this thread adding your files as attachments - see manage attachments button or send them to keith.m.brown@tesco.net
 

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