download tanner tools
as I remember , in Linux eda enviroment (RHEL) , we usually use Laker /Virtuso ., we never use Windows base layout tool , Tanner can be use just for small company or student ,
many foundry (Fabs) support DRC/Lvs command file only dracula/calibre or tech file , not for
ledit , you need write it by yourself , just like Korea EDA mychips ( windows OS base fully layout tools just like Ledit)
in cell base design (digital circuit design) , we only use "verilog netlist "
from RTL -> logic synthesis (Synopsys tool) ->
gate level verilog netlost
and P&R in Linux workstation , usually > 100K gate
, ledit SPR not support "verilog" netlist .
maybe some tool can convert Verilog-to-EDIF
but , I hope Ledit SPR can support verilog format in the future .