I need help with VHDL register

i wondering how create a register in witch i can write 4bits A input and 4bits B input. then take these data from register and sum them. sorry for my english

use of concatenation operator will solve your problem.
You will need the 8 bit wide signal to be declared and assigne the values of A and B using concatenation operator.

by using carry lookahead generator coding u can done wht u want...each input must of 4 bits

if (addr of A) and (write_en = 1)
A(3 downto 0) <= data(3 downto 0)
if (addr of B) and (write_en = 1)
B(3 downto 0) <= data(3 downto 0)

--To concatenate the input A and B
C(7 downto 0) <= A & B;
-- To sum the inputs A and B
D(4 downto 0) <= A+B;

thx for help, but I need more help

I need creat a register ARCHITECTURE and adder ARCHITECTURE in same project, Xr and Yr must be taken from register

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY r3g IS
PORT (X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Xr, Yr : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
Clock, Reset : IN STD_LOGIC);
END r3g;

ARCHITECTURE Behavior OF r3g IS
BEGIN
PROCESS ( Reset, Clock )
BEGIN
IF Reset = '1' THEN
Xr <= (OTHERS => '0'); Yr <= (OTHERS => '0');
ELSIF Clock'EVENT AND Clock = '1' THEN
Xr <= X; Yr <= Y;
END IF ;
END PROCESS ;
END Behavior;

-------------------------------------------------------------------------

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY sum IS
PORT ( Xr, Yr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END sum;
ARCHITECTURE Behavior OF sum IS
BEGIN
D <= Xr+Yr;
END Behavior;