I need help to write XORs in VHDL, thanks

[program]

Hi every one

I wrote the VHDL code for the following equations so that we get a new value for b every clock cycle .
Please any body know how to rewrite this equation so that increase the speed of the design (frequency).

a : in std_logic_vector (11 downto 0);
b : out std_logic_vector (11 downto 0);

b(0) <= a(0) xor a(2) xor a(4) xor a(5) xor a(6) xor a(7) xor a(8) xor a(9) xor a(10) xor a(11) ;
b(1) <= a(2) xor a(4) ;
b(2) <= a(3) xor a(5) ;
b(3) <= a(4) xor a(6) ;
b(4) <= a(5) xor a(7) ;
b(5) <= a(6) xor a(8) ;
b(6) <= a(0) xor a(7) xor a(9) ;
b(7) <= a(1) xor a(8) xor a(10) ;
b(8) <= a(2) xor a(9) xor a(11) ;
b(9) <= a(0) xor a(1) xor a(3) xor a(4) xor a(5) xor a(6) xor a(7) xor a(8) xor a(9) xor a(11) ;
b(10) <= a(0) xor a(2) xor a(11) ;
b(11) <= a(0) xor a(3) xor a(4) xor a(5) xor a(6) xor a(7) xor a(8) xor a(9) xor a(10) xor a(11) ;



Thanks in advance

 

[rca]

When you indicates to increase the speed, did you have some issue during the synthesis?
the only way to reduce the speed is to add pipeline. The synthesis will try to reach the frequency request as possible and will change the logic.

 

[program]

Thanks rca for replay, the design was synthesised without problem, but I meant if we can arrange the XORs in somehow to get max frequency,e,g take the similar signal aside such as a(9) and a(10).

 

[rca]

I beleived the xor equation is the optimal. the synthesis will look at this to find a slowest logic.
you could try to increase the synthesis frequency to know, what are the limit and the margin.

 

[program]

Thanks rca, I agree with you.

 

[wsong0210]

say your current can run at 50MHz.
What your circuit do is to calculat b(n+1) from a
I dont know what happen to a, is it updated by b?
Anyway, if you can figure out the equation of calculating b(n+2) from a,
you can calculate this in two cycles, which is equivalent to the original one.
As a result, the new equation needs to run at 25MHz but normally it can be fater than 25 MHz as no registers in the pipeline.
Instead of reducing your clock, this part can be constrained as multi-cycle path and the output is registered every other cycle. Hopfully the circuit can run at 60MHz if the equation can run at 30MHz.

The other way, also calculate the new equation, and make it extra.
Then in every cycle you can calculate b(n+1) and b(n+2) both from a. After that, you may be able to save some clocks doing others thing which may help speed.

Anyway, what I am trying to say, in extreme cases, when synthesis can not meet the speed target, we can change circuit structure, make more parallelism and do retiming to speed up.