I need help on ESD protection

[lylnk]

I have designed a high voltage detection circuir. The input high voltage can be 0v~16v. I use two poly resistors to divide input high voltage to 0~3v. The total resistance of resistors is about 200kohm. The circuit is fabricated upon 3.3v process.
There is a question on the ESD protection of high voltage input pin.
There is no active device can withstand 16v. I have not find any device, whose bread down voltage exceed 12V, except NW/PSUB diode. The typical break down voltage of NW diode is 14V. I think the minimum break voltage will be less than 12V.
The field oxide under poly is about 350nm. It is deposited perhaps. I think the break down voltage of the oxide is about 200V.

How can i survive under 2kv human body ESD model? I need help.
Will the ESD damage the field oxide?

 

[DenisMark]

Don't use reverse biased diodes as ESD protection element. Their have very small current capability during ESD stress.
U'll need devices with snapback action like TFO (thick field oxide) or GGNMOS (gate grounded NMOS), GGPMOS. If their breakdown voltage less than 16V use them in series (stack).
Only foundary can helps u regarding snapback properties of devices in ur process.

 

[leo_o2]

Yes, I agree. And the field oxide will be weak if there is no ESD discharging path. The breakdown voltage of field oxide would never be as high as 200V!!!

 

[lylnk]

I don't know how to draw a good field nmos.
The field nmos uses nwell as source and drain. The gate oxide is field oxide.
If the distance of source and drain is too large, the resistance will be large; if the distance of source and drain is too small, the depletion of source and drain will touch each other under normal voltage(16v).

If the distance L1 fulfil 6V, should i use 1.7*L1 to fufill 1.7*1.7*6=17.34V?

If I use the VTH of field nmos, the VTH should be higher than 16V. Is the VTH of field nmos of 0.18um 1.8v/3.3v process higher enough?
Should I use the break voltage BVDS of field nmos? Is it higher than 16V?

Can the foundry give me some suggestion?

 

[lylnk]

Does the filed oxide nmos aganst ESD like a NPN?

 

[suru]

Message is unavailable.

 

[leo_o2]

Usually 3~5um is used for NMOS drain contact spacing to channel.

 

[prcken]

usually, the SCR based ESD protection device has high triggering voltage, but you should consider the oxide breakdown problem in your input mosfet, so how to protect your inner ckt while trigger you ESD device in time ? think about it, sometimes we can use a secondary protection device behind a series resistance