i need boot fpga with the microprocessor

[zula]

Hi, iam workin on configuring fpga with the external uP. is there any reference design and reference code?
i want to directly boot configuration data into fpga with uP. or i must boot configuration data into PROM and then fpga?

is here anyone working like this peoject please help me.

thanks for reply.

 

[Brownout]

FPGA's can read prom directly, so there is no need for usig a uP.

 

[zula]

i know it but i will boot fpga via ethernet. because of that i have to use a uP.

 

[alexan_e]

these may help

**broken link removed** (download the pdf and code)

Alex

 

[amitjagtap]

I have worked on this. FPGA configuration using uP and CPLD.
I think Xilinx Application note XAPP 502 will be useful to you.
Well, FPGA can read cong data directly from PROM. It can use Xilinx platform flash or some third party flash.

---------- Post added at 07:53 ---------- Previous post was at 07:51 ----------

I have worked on this. FPGA configuration using uP and CPLD.
I think Xilinx Application note XAPP 502 will be useful to you.
Well, FPGA can read cong data directly from PROM. It can use Xilinx platform flash or some third party flash.

 

[lucbra]

I know that Lattice had (or has) something that calls ispVM embedded (it's freeware). That's what you need.
It's a piece of C-code that you can integrate in your µC to build the interface to the FPGA (JTAG, ISP, ...).
You have to upload from the Ethernet to a memory bank in the µC, and from there you can download into the FPGA.
It's a technique commonly used in the past when PROM were very pricy.

 

[zula]

@lucbra, unfotunately we will use xilinxs fpgas.

@amitjagtap, i readed app. notes but iam not sure that really need a CPLD? iam looking for a solution like this, there must be a PROM, FPGA, and uP. I will boot the conf. data into prom by uP. After that i will reset the system and when fpga wake up it will read a new conf. data?

 

[FvM]

Of course, a uP is capable of configuring SRAM based FPGAs from any manufacturer without additional hardware, either using JTAG or vendor specific serial and parallel configuration interfaces of the specific FPGA family. You have to know, if the configuration bit stream size fit's the uP's internal flash memory, or if you have to provide an external memory, e.g. a serial SPI flash to store the configuration.

As far I'm aware of, direct configuration by a uP is the mostly used method, if a suitable uP is present in the system. If it isn't, hardware based configuration comes into play.

 

[zula]

thanks for your reply fvm. one more question, you are mentione SPI. is this a standart SPI? i mean when i tried to use uP which include SPI module, and SPI flash it will be enough? should i write extra codes about SPI functions in the uP?

 

[FvM]

I'm using Micron (former Numonyx, former ST) M25P04 and similar SPI flash devices with uP built-in hardware SPI. It's easy.

 

[zula]

thanks a lot.

 

[alexan_e]

Also take a look at www.xilinx.com/support/documentation/application_notes/xapp800.pdf

This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and
Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.
These devices are physically small with low-pin count, small outline packages. Using a
CoolRunner™-II CPLD, the SPI bus and protocol are converted to those which are used by the
FPGA for configuration, specifically Master Serial configuration.

Alex

 

[lucbra]

@lucbra, unfotunately we will use xilinxs fpgas.

That shouldn't be a problem. The code is for the uC and if I remember well, vendor independent. Like FvM mentioned, it implements a JTAG interface.
If you have a nice processor (I guess you have as you are trying to implement a Ethernet based system) you can download the FPGA firmware in RAM and then pass it through to the FPGA. Usually, the firmware is secured in a Flash (SPI or parallel whatever is available).

@FvM I'm not sure that the majority of the FPGA's are configured through a microcontroller, but I'm not going to start a discussion about it. Maybe a good idea for a poll?

Best regards

 

[permute]

Just look at the configuration guide for the FPGA you are using. for example, xilinx has a "slave serial" which is SPI-like. But it is different as there is no CS line. This can be an issue if you need to access another SPI device with the same SPI controller during the programming process. The init_b/prog_b/done lines are also not in the SPI spec. but a SPI capable uC can be used to generate the correct clk/data transmission, leaving the init/prog/done lines to be used with bit-banging. As long as you don't need to bit-bang the clk/data lines, you should be fine.

Likewise, bigger processors can use the slave "select-map" interface to write 8b/16b/32b at a time to the FPGA, and this can allow the FPGA to be programmed quickly. IIRC, you can set up some EBI interfaces to efficiently access this bus.

JTAG interfaces can also be used, but the speed of programming will probably be less than a dedicated SPI bus, and certainly less than the high-speed parallel interfaces, especially if the uC has to resort to bit-banging the data/clk lines. These choices make the difference between 0.3s, 3s, and 30s+ program times. (sub-second programming typically requires a fast data source or fast decompression of a compressed core). It may be useful to include a JTAG option, as JTAG is still useful for other purposes.

You can also program flash, and then use the FPGA's master serial/select-map. this works well if the FPGA will nearly always use the same configuration as the flash can be made high speed, and the system can program very quickly at boot. In your case, it at least allows the FPGA to load if no ethernet connection is available. It might also be useful for large FPGA's used in PCIe applications that need to meet the fast-boot part of the PCIe spec.

A separate flash is not needed for slave-serial/select-map unless the uC code needs to be stored in an external flash.

 

[amitjagtap]

Zula, Off-course you can use only uP to configure FPGA. Low cost CPLD used in most of the cases where uP i/Os are not sufficient. You can use JTAG to configure FPGA through uP. But you have to have JTAG control to send a bit file over JTAG. The Simplest one is using "Slave select Serial Configuration mode" of the FPGA. In which some uP GPIOs will be used and thus easy to implement. Well its bitter to go through the configuation guide of peryicular FPGA. All things are there mentioned in detail.

 

[XDesigner]

Amitjagtap, I want to configure FPGA with PowerPC 440 processor (i use Gpio to connect JTAG signals). Can you show me how connect Gpio to JTAG interface and
do you have some C code to configure FPGA by PowerPC440? thanks.