I need a quick Synopsys Design Compiler tutorial!

[energeticdin]

tutorial synopsys

I think this may be useful for all begineers

 

[vlsichipdesigner]

tutoriel design compiler

hi,

my 2 cents to your problem.

This link explains about the Synthesis reference flow.
https://www.vlsichipdesign.com/asicsynthesisflow.html

There is a reference script template file is available in the below mentioned link
https://www.vlsichipdesign.com/synopsys_constraints.html

All the information are available for Free access no need of any membership or login, for the benefit of the chip design community...

Best regards,
vlsichipdesigner
https://www.vlsichipdesign.com

 

[boardlanguage]

design compiler synopsys tutorial

For beginners, Design Compiler is difficult to learn for the following reasons:

1) requires background in the ASIC design flow (RTL synthesis -> gate -> place & route -> Clock-tree insertion -> detailed route -> DRC/LVS )

2) Design Compiler itself, only does the first activity, but gas many features to 'help' downstream tools (i.e. gate and beyond)

3) The documentation isn't perfectly clear about the boundaries between steps, because that's dependent on your company's tool environment. Some companies use Design Compiler and then hand-off the netlist to a design-services bureau. Others do everything in-house.

All I can say is that Synopsys runs some training workshops -- to help people get started with Design Compiler. This will not make you an expert -- you'll still need to practice and study on your own. But it might help people who are 'stuck' at the very beginning. Synopsys charges a lot of $$$ for those workshops -- so you need to mentally make a commitment to learn the tool.

Let me just say, some of the workshops are not very helpful. Quite simply, Synposys presents the 'mainstream usage model' for their tools. If your company deviates from that model, even in the slightest, you might just get even more confused.

Good luck!

 

[sargu]

synopsys lab document

HI,

Can anyone tell me if there is any way i can get help on errors and warning in DC

I got some warning in the check_design report and check _timing report, I want to know why they are occuring and how to remove that...

I heard that some tools will have such help. When we type help <error id>, it will give the reason for it and the what is to be done..

I tried this in DC, but it dint work.

Can someone please guide me on this...

Or point me to a document/site or anything from where I can get help on this.

Thanks in advance